Sampling pulse generator

Abstract

A sampling pulse generator utilizes sampling clocks CLi each having a frequency which corresponds to a character data signal D to be sampled. Each phase of these clocks CLi is progressively and slightly deviated from one another. One of these clocks CLi will be in-phase with the signal D. A feedback signal P1 corresponding to one of these clocks CLi is phase-compared with a clock run-in signal CR which is used as the phase reference of signal D. If signal P1 leads signal CR in phase, the suffix "i" of CLi is incremented, while the suffix "i" is decremented if signal P1 lags in phase behind signal CR. By the change of suffix "i" of clocks CLi, the phase difference between signals P1 and CR is minimized. One of the sampling clocks CLi thus obtained is used as a sampling pulse output SP of the sampling pulse generator which is substantially in-phase with the signal CR or D.

What is claimed is: 
     
       1. A sampling pulse generator for use in sampling a character or symbolic data signal in a transmitted data signal, said symbolic data signal containing a clock run-in signal which is used as a phase reference of this symbolic data signal, said sampling pulse generator comprising: signal source means for generating a reference signal having a frequency corresponding to the frequency of said symbolic data signal to be samplied;   delay means coupled to said signal source means, for delaying said reference signal and providing a plurality of sampling clocks, the frequency of each of said sampling clocks being equal to the frequency of said reference signal, and each phase of said sampling clocks with respect to said reference signal having an individual value;   selector means coupled to said delay means and being responsive to designation data, for selecting a smpling pulse output from said sampling clocks according to the content of said designation data;   designation means coupled to said selector means and being responsive to gate data, for generating said designation data such that the content of said designation data is incremented or decremented according to the content of said gate data; and   comparator means coupled to said selector means and to said designation means, for generating a feedback signal which is in-phase and synchronized with said sampling pulse output, and for comparing the phase of said feedback signal with that of said clock run-in signal and generating said gate data according to the result of comparison, said selector means selecting a particular one of said sampling clocks based on the result of comparison in said comparator means, so that the phase difference between said feedback signal and said clock run-in signal becomes minimum and the selected particular one of said sampling clocks is used as said sampling pulse output;   said selector means, designation means and comparator means jointly forming a closed negative feedback loop which operates to minimize the phase difference between said feedback signal and said clock run-in signal which is the control target of said feedback loop;   said closed negative feedback loop including means responsive to an on/off instruction, for opening said closed feedback loop when the content of said on/off instruction indicates the "off" of the negative feedback operation, so that the content of said designation data is fixed, said feedback loop being closed when the content of said on/off instruction indicates the "on" of the negative feedback operation.   
     
     
       2. A sampling pulse generator for use in sampling a character or symbolic data signal in a serially transmitted data signal, said symbolic data signal containing a clock run-in signal which is used as a phase reference of this symbolic data signal, said sampling pulse generator comprising: means for generating a pulse train having a bit rate corresponding to the bit rate of said symbolic data signal;   delay means coupled to said generating means, for delaying said pulse train and providing a plurality of delayed signals in such a way that each phase of said delayed signals with respect to said pulse train has an individual value;   selector means coupled to said delay means, for selecting one of said delayed signals as a data sampling pulse;   detector means coupled to said selected means and being responsive to said clock run-in signal, for detecting the phase difference between the selected one of said delayed signals with that of said clock run-in signal and providing a control signal; and   control means coupled to said selector means and said detector means, for controlling said selector means according to said control signal, such that the phase difference between said selected one delayed signal and said clock run-in signal becomes minimum;   said detector means including: means for extracting from said symbolic data signal a reference phase signal corresponding to said clock run-in signal;   comparator means coupled to said extracting means and said selector means, for comparing the phase difference between said selected one delayed signal and said reference phase signal and providing a comparison result; and   means coupled to said comparator means and said control means, for producing said control signal from said comparison result and said clock run-in signal.     
     
     
       3. A generator according to claim 1, wherein said comparator means includes: a first frequency converter for converting the frequency of said sampling pulse output into the frequency of said feedback signal, and providing the conversion result as said feedback signal;   a phase comparator for comparing the phases of said feedback signal and clock run-in signal, generating a first gate signal when said feedback signal is leading said clock run-in signal in phase, and generating a second gate signal when said feedback signal is lagging in phase behind said clock run-in signal, said first and second gate signals constituting said gate data, and   wherein said first gate signal is generated for incrementing the content of said designation data and said second gate signal is generated for decrementing the content of said designation data.   
     
     
       4. A generator according to claim 3, wherein said phase comparator includes: a second frequency converter for converting the frequency of said clock run-in signal into the frequency of said sampling pulse output, and generating a clock signal having the same frequency as that of said sampling pulse output; and   a D type flip-flop receiving at its D input said feedback signal and being clocked by said clock signal, and generating said first and second gate signals from its Q and inverted Q outputs.   
     
     
       5. A generator according to claim 4, wherein said designation means includes: a gate circuit responsive to said data signal and gate data, for providing an up count signal being synchronized with said data signal when said gate data is said first gate signal, and providing a down count signal being synchronized with said data signal when said gate data is said second gate signal; and   an up/down counter for up-counting said up count signal when said gate data is said first gate signal, and for down-counting said down count signal when said gate data is said second gate signal, the count result of said up/down counter being used as said designation data.   
     
     
       6. A generator according to claim 4, wherein said delay means is provided with a third frequency converter responsive to a subcarrier signal having a color subcarrier frequency of TV system, for converting said subcarrier signal into the frequency of said reference signal, and wherein said data signal includes character information of a teletext or videotex system, the frequency of which information is the half of the frequency of said sampling pulse output.   
     
     
       7. A generator according to claim 5, wherein said gate circuit includes: a first AND gate for providing a first output corresponding to the logical AND of said second gate signal and said data signal;   a second AND gate for providing a second output corresponding to the logical AND of said first gate signal and said data signal;   a third AND gate for providing a third output corresponding to the logical AND of said second gate signal and an inverted signal of said data signal;   a fourth AND gate for providing a fourth output corresponding to the logical AND of said first gate signal and said inverted signal;   a first OR gate coupled to said second and third AND gates, for providing said up count signal corresponding to the logical OR of said second and third outputs; and   a second OR gate coupled to said first and fourth AND gates, for providing said down count signal corresponding to the logical OR of said first and fourth outputs.   
     
     
       8. A generator according to claim 7, wherein said gate circuit further includes: a fifth AND gate responsive to a clock signal having the same frequency as that of said sampling pulse output and to a clock gate signal, for providing a clock pulse corresponding to the logical AND of said clock signal and clock gate signal, and   wherein said clock pulse is supplied as an AND input signal to each of said first to fourth AND gates, the frequency of said clock pulse defining the counting rate of said up/down counter.   
     
     
       9. A generator according to claim 4, wherein said second frequency converter is a frequency doubler and includes: a delay element for delaying said clock run-in signal by a given time to provide a delayed signal;   a gate responsive to said delayed signal and clock run-in signal, for generating said clock signal when the logical level of said delayed signal is opposite to that of said clock run-in signal.   
     
     
       10. A sampling pulse generator for use in sampling a character or symbolic data signal in a transmitted data signal, said symbolic data signal containing a clock run-in signal which is used as a phase reference of this symbolic data signal, said sampling pulse generator comprising: signal source means for generating a reference signal having a frequency corresponding to the frequency of said symbolic data signal to be sampled;   delay means coupled to said signal source means, for delaying said reference signal and providing a plurality of sampling clocks, the frequency of each of said sampling clocks being equal to the frequency of said reference signal, and each phase of said sampling clocks with respect to said reference signal having an individual value;   selector means coupled to said delay means and being responsive to designation data, for selecting a sampling pulse output from said sampling clocks according to the content of said designation data;   designation means coupled to said selector means and being responsive to gate data, for generating said designation data such that the content of said designation data is incremented or decremented according to the content of said gate data; and   comparator means coupled to said selector means and to said designation means, for generating a feedback signal which is in-phase and synchronized with said sampling pulse output, and for comparing the phase of said feedback signal with that of said clock run-in signal and generating said gate data according to the result of comparison, said selector means selecting a particular one of said sampling clocks based on the result of comparison in said comparator means, so that the phase difference between said feedback signal and said clock run-in signal becomes minimum and the selected particular one of said sampling clocks is used as said sampling pulse output;   said comparator means including: a first frequency converter for converting the frequency of said sampling pulse output into the frequency of said feedback signal, and providing the conversion result as said feedback signal;   a phase comparator for comparing the phases of said feedback signal and clock run-in signal, generating a first gate signal when said feedback signal is leading said clock run-in signal in phase, and generating a second gate signal when said feedback signal is lagging in phase behind said clock run-in signal, said first and second gate signals constituting said gate data; and   wherein said first gate signal is generated for incrementing the content of said designation data and said second gate signal is generated for decrementing the content of said designation data;   said phase comparator including: a second frequency converter for converting the frequency of said clock run-in signal into the frequency of said sampling pulse output, and generating a clock signal having the same frequency as that of said sampling pulse output; and   a D type flip-flop receiving at its D input said feedback signal and being clocked by said clock signal, and generating said first and second gate signals from its Q and inverted Q outputs.       
     
     
       11. A generator according to claim 10, wherein said designation means includes: a gate circuit responsive to said data signal and gate data, for providing an up count signal being synchronized with said data signal when said gate data is said first gate signal, and providing a down count signal being synchronized with said data signal when said gate data is said second gate signal; and   an up/down counter for up-counting said up count signal when said gate data is said first gate signal, and for down-counting said down count signal when said gate data is said second gate signal, the count result of said up/down counter being used as said designation data.   
     
     
       12. A generator according to claim 10, wherein said delay means is provided with a third frequency converter responsive to a subcarrier signal having a color subcarrier frequency of TV system, for converting said subcarrier signal into the frequency of said reference signal, and wherein said data signal includes character information of a teletext or videotex system, the frequency of which information is the half of the frequency of said sampling pulse output.   
     
     
       13. A generator according to claim 11, wherein said gate circuit includes: a first AND gate for providing a first output corresponding to the logical AND of said second gate signal and said data signal;   a second AND gate for providing a second output corresponding to the logical AND of said first gate signal and said data signal;   a third AND gate for providing a third output corresponding to the logical AND of said second gate signal and an inverted signal of said data signal;   a fourth AND gate for providing a fourth output corresponding to the logical AND of said first gate signal and said inverted signal;   a first OR gate coupled to said second and third AND gates, for providing said up count signal corresponding to the logical OR of said second and third outputs; and   a second OR gate coupled to said first and fourth AND gates, for providing said down count signal corresponding to the logical OR of said first and fourth output.   
     
     
       14. A generator according to claim 13, wherein said gate circuit further includes: a fifth AND gate responsive to a clock signal having the same frequency as that of said sampling pulse output and to a clock gate signal, for providing a clock pulse corresponding to the logical AND of said clock signal and clock gate signal, and   wherein said clock pulse is supplied as an AND input signal to each of said first to fourth AND gates, the frequency of said clock pulse defining the counting rate of said up/down counter.   
     
     
       15. A generator according to claim 10, wherein said second frequency converter is a frequency doubler and includes: a delay element for delaying said clock run-in signal by a given time to provide a delayed signal;   a gate responsive to said delayed signal and clock run-in signal, for generating said clock signal when the logical level of said delayed signal is opposite to that of said clock run-in signal.   
     
     
       16. A generator according to claim 10, wherein said selector means, designation means and comparator means jointly form a closed negative feedback loop which operates to minimize the phase difference between said feedback signal and said clock run-in signal which is the control target of said feedback loop. 
     
     
       17. A generator according to claim 2, wherein said delay means includes a delay line having a plurarity of taps from which said delayed signals are outputted; said control means includes an up/down counter for up or down counting said control signal, the counted result of said up/down counter determining the selection of said delayed signals at said selector means;   said comparator means includes a D type flip-flop whose D input receives a D input signal corresponding to said selected one delayed signal, whose clock input receives said reference phase signal, whose output provides a first comparison result and whose inverted output provides a second comparison result, said first and second comparison results being used as said comparison result; and   said producing means includes a logic circuit responsive to said first and second comparison results and to said clock run-in signal, for providing an up count pulse according to said first comparison result and said clock run-in signal, and for providing a down count pulse according to said second comparison result and said clock run-in signal, said up and down count pulses being used as said control signal.   
     
     
       18. A generator according to claim 17, wherein said extracting means includes: a delay element for delaying said symbolic data signal and providing a delayed data signal; and   an EXOR gate whose one input receives said symbolic data signal, whose another input receives said delayed data signal and whose output provides said reference phase signal, and   said comparator means further includes a frequency divider for dividing the frequency of said selected one delayed signal by 2 and generating said D input signal (P1).