Semiconductor device

Abstract

The invention relates to an EPROM or an EEPROM in which the information is stored in the form of electrical charge above the channel region of a MOST, as a result of which the threshold voltage of the MOST is determined by the stored information. Writing/erasing of the memory generally requires high voltages to cause charge current to flow through an insulating layer to and from the charge storage region. In order to avoid having the parasitic MOSTs becoming conductive, means are provided by which during operation a small reverse bias is applied to the sources of these parasitic transistors, as a result of which due to the high k factor the threshold voltage of the parasitic transistors increases considerably. This does not require additional logic because use can be made of the generator in the reading circuit, which generates a suitable small voltage.

What is claimed is: 
     
       1. A semiconductor device comprising a semiconductor body having a major surface, a non-volatile memory at said surface and having a plurality of memory cells, each memory cell comprising an insulated gate field effect transistor having a channel region, an insulating layer covering said channel region, a charge storage region defined in said insulating layer, the threshold voltage of said transistor being determined by the electrical charge stored in said charge storage region, said transistor further comprising a gate electrode which is capacitively coupled to said charge storage region and source and drain zones of a first conductivity type, a layer-shaped part of the semiconductor body of the second conductivity type surrounding said source and drain zones, a p-n junction separating said source and drain zones from said layer-shaped part of the second conductivity type, means for applying a voltage to said layer-shaped part of the semiconductor body during operation, a conductive region adjoining said insulating layer, and means for applying a voltage difference between said gate electrode and said conductive region during at least one of erasing and writing such that an electrical field is produced across said insulating layer so that a charge flow can occur between said charge storage region and said conductive region, means for applying an at least substantially constant voltage to at least one of the source and drain zones of the transistor during at least one of erasing and writing such that the p-n junction between said at least one zone and the layer-shaped part of the semiconductor body is reversely biased during the whole of said at least one erasing or writing cycle to avoid the formation of parasitic channels adjoining said at least one zone, said voltage across said last-recited p-n junction being lower than said voltage difference which is applied between the gate electrode and the conductive region for producing the charge flow between the charge storage region and the conductive region. 
     
     
       2. A semiconductor device as claimed in claim 1, characterized in that during at least one erasing and writing the same voltage is applied to said zone as during reading, in order to prevent the formation of parasitic channels adjoining that zone. 
     
     
       3. A semiconductor device as claimed in claim 1, or claim 2, characterized in that the conductive region adjoining the insulating layer is a a substrate region of the semiconductor body located under the charge storage region. 
     
     
       4. A semiconductor device as claimed in claim 3, characterized in that the charge storage region comprises a floating gate electrode, which is embedded in the insulating layer between the gate electrode and the surface of the semiconductor body and extends above one of the source and drain zones of the transistor, which zone also comprises said substrate region which is used for applying at least one of an erasing voltage and a programming voltage. 
     
     
       5. A semiconductor device as claimed in claim 4, characterized in that the floating gate is separated from said zone by an insulating layer which is so thin that at least one of writing and erasing takes place at least substantially via quantum tunnelling mechanisms. 
     
     
       6. A semiconductor device as claimed in claim 2, characterized in that means are provided by which the other zone of the transistor is caused to float electrically during at least one of erasing and writing.