Programmable image processor

Abstract

Disclosed is an image processor that processes desired image data according to a program. In the image processor, the addressing desired pixels which is stored in an image memory is performed by an address processor, and a partial image taken out of the image memory by the address processor is written into a shared memory, and then data is drawn out from the shared memory by an operational processor to carry out operational processing. The address processor is provided with a buffer memory in which image data in a predetermined area is stored and successively renewed by an increment/decrement designation for read and write operations.

What is claimed is: 
     
       1. A programmable image processor, comprising: an image memory for digitizing and storing image data;   an address processor adapted to effect addressing with respect to desired pixels on said image memory and draw out the corresponding pixel data on desired portions;   a shared memory into which pixel data on said desired portions are successively written by said address processor; and   an operational processor adapted to receive the pixel data stored in said shared memory for each of said desired portions and successively effect necessary scanning and processing of the pixel data;   said shared memory being simultaneously accessible by said address processor and said operational processor to perform one read and one write operation on said pixel data during each processing cycle of said address processor and operational processor.   
     
     
       2. An image processor according to claim 1, wherein said address processor further comprises a buffer memory operatively interconnected between said image memory and shared memory, said buffer memory being adapted to receive from said image memory pixel data on a set of repetitively referred to pixels and to store the same and set said repetitively referred to data in said shared memory. 
     
     
       3. An image processor according to claim 2, further comprising an address register for effecting address control of said buffer memory and perform read and write operations on said buffer memory by effecting an arithmetic change on the address of a memory location containing data about a first pixel to which attention is being paid and thereby obtain an address of a memory location containing data about a second pixel adjacent to said first pixel. 
     
     
       4. An image processor according to claim 1, wherein said shared memory can be addressed independently by both of said address processor and said operational processor, and has a mechanism capable of arithmetically changing an address in accordance with one of a read or write operation. 
     
     
       5. An image processor according to claim 1, further comprising: an instruction word memory discrete from said image memory for storing a processing program separately from said image data; and   a mechanism adapted to be able to read out subsequent instruction data from said instruction word memory while operating upon said image data in accordance with a preceding instruction.   
     
     
       6. An image processor according to claim 1, further comprising means for controlling said address processor and operational processor, including means for effecting the execution of instruction words sequentially and taking out and decoding instruction words after a conditional branch instruction is issued, and for giving priority to decoding the branch side of each of said instruction words. 
     
     
       7. An image processor according to claim 1, further comprising: a loop counter for controlling the repetition of read/write operations with respect to said image memory and a plurality of other operations; and   means for executing an instruction repetitively in a number of instruction cycles determined by the count processing of said loop counter.   
     
     
       8. A programmable image processor comprising: an image memory that scans a desired screen area in a predetermined pixel number and stores image data from each of a plurality of pixels in a scanning order;   an address processor for effecting addressing of said image memory for desired pixels and taking out image data on desired portions from said image memory, said address processor having, as an address register with respect to said image memory, an index register capable of performing arithmetic operations according to an increment/decrement designation for generation of addresses of pixels, adjoining a pixel to which attention is being paid;   a shared memory accessible by said address processor for transferring image data from said address processor; and   an operational processor for accessing said shared memory sumiltaneously with said address processor and for effecting data processing with respect to said image data on said desired portions.   
     
     
       9. A programmable image processor according to claim 8, wherein said index register is constituted by a plurality of up/down counters interconnected in a cascade configuration to receive ripple-through carry signals. 
     
     
       10. A programmable image processor according to claim 8, wherein said address processor further comprises a buffer memory operatively interconnected between said image memory and said shared memory, said buffer memory being suitable for performing processes of receiving said image data from said image memory, and said address register being coupled to said buffer memory and conducting read and write operations on said buffer memory after performing said arithmetic operations. 
     
     
       11. An image processor according to claim 10, wherein said buffer memory and said address register are each controllable by said address processor to simultaneously complete one of said processes and operations, respectively. 
     
     
       12. An image processor according to claim 10, wherein said buffer memory has a lesser memory capacity than said image memory. 
     
     
       13. An image processor according to claim 12, wherein said shared memory has a lesser memory capacity than said buffer memory. 
     
     
       14. An image processor according to claim 10, wherein said shared memory can be addressed independently by both of said address processor and said operational processor. 
     
     
       15. An image processor according to claim 14, further comprising: an instruction word memory discrete from said image memory for storing a processing program separately from said image data; and   a mechanism suitable for reading out a subsequent instruction from said instruction word memory while operating upon said image data in accordance with a preceding instruction.   
     
     
       16. An image processor according to claim 8, further comprising means for controlling said address processor and operational processor, including means for effecting execution of instruction words sequentially and taking out and decoding instruction words after a conditional branch instruction is issued, and for giving priority to decoding the branch side of each of said instruction words. 
     
     
       17. An image processor according to claim 8, further comprising: a loop counter for controlling the repetition of read/write operations with respect to said image memory and a plurality of other operations; and   means for executing an instruction repetitively in a number of instruction cycles determined by the count processing of said loop counter.   
     
     
       18. A programmable image processor, comprising: an image memory for digitizing and storing image data from a plurality of pixels;   an address processor suitable to effect addressing of said image memory to obtain image data on selected ones of said pixels;   a shared memory into which said image data from desired portions of said image memory is successively written by said address processor;   said address processor including a buffer memory interconnected between said image memory and shared memory, said buffer memory being suitable to perform the processes of receiving from said image memory data on a set of repetitively referred to portions of said image memory, storing said data from said repetitively referred to portions, and setting in said shared memory said data from said repetitively referred to portions, and an address register for effecting address control of said buffer memory and for performing read and write operations on said buffer memory by completing arithmetic changes of address;   an operational processor adopted to receive said image data stored in said shared memory for each of said desired portions and successively effect scanning of said image memory and processing of said image data; and   said shared memory being simultaneously accessible by said address processor and said operational processor to perform one read and one write operation during one processing cycle of said address processor and operational processor.   
     
     
       19. An image processor according to claim 18, wherein said buffer memory and said address register are controllable by said address processor to both simultaneously complete one of said processes and operations, respectively. 
     
     
       20. An image processor according to claim 19, wherein said buffer memory has a lesser memory capacity than said image memory. 
     
     
       21. An image processor according to claim 20, wherein said shared memory has a lesser memory capacity than said buffer memory. 
     
     
       22. A programmable image processor, comprising: an image memory for digitizing and storing image data;   an address processor adapted to effect addressing with respect to desired pixels on said image memory and draw out the corresponding pixel data on desired portions;   a shared memory into which pixel data on said desired portions is successively written by said address processor;   an operational processor adapted to receive the pixel data stored in said shared memory for each of said desired portions and successively effect scanning and processing of said pixel data; and   means for controlling said address processor and operational processor, including means for effecting the execution of instruction words sequentially and taking out and decoding instruction words after a conditional branch instruction is issued, and for giving priority to decoding the branch side of each of said instruction words.   
     
     
       23. An image processor according to claim 22, wherein said address processor has, as an address register with respect to said image memory, an index register capable of performing arithmetic operations according to an increment/decrement designation for generation of addresses of pixels adjoining a pixel to which attention is being paid. 
     
     
       24. A programmable image processor according to claim 23, wherein said address processor further comprises a buffer memory operatively interconnected between said image memory and said shared memory, said buffer memory being suitable for performing processes of receiving said image memory, and said address register being coupled to said buffer memory for effecting address control of said buffer memory and conducting read and write operations on said buffer memory after performing said arithmetic operations. 
     
     
       25. A programmable image processor, comprising: an image memory for digitizing and storing image data;   an address processor adapted to effect addressing with respect to desired pixels on said image memory and draw out the corresponding pixel data on desired portions;   a shared memory into which pixel data on said desired portions is successively written by said address processor;   an operational processor adapted to receive the pixel data stored in said shared memory for each of said desired portions and successively execute scanning and processing of said pixel data;   a loop counter for controlling the repetition of read/write operations with respect to said image memory and a plurality of other operations; and   means for executing an instruction repetitively in a number of instruction cycles determined by the count processing of said loop counter.   
     
     
       26. An image processor according to claim 25, wherein said address processor has, as an adddress register with respect to said image memory, an index register capable of performing arithmetic operations according to an increment/decrement designation for generation of addresses of pixels adjoining a pixel to which attention is being paid. 
     
     
       27. A programmable image processor according to claim 26, wherein said address processor further comprises a buffer memory operatively interconnected between said image memory and said shared memory, said buffer memory being suitable for receiving image data from said image memory, and said address register being coupled to said buffer memory for effecting address control of said buffer memory and conducting read and write operations on said buffer memory after performing said arithmetic operations. 
     
     
       28. A programmable image processor, comprising: image memory means for scanning a desired screen area in a predetermined pixel member and storing image data for each of a plurality of pixels in a scanning order;   an address processor for effecting addressing of said image memory for desired pixels and taking out image data on desired portions from said image memory, said address processor having, as an address register with respect to said image memory, an index register capable of performing arithmetic operations according to an increment/decrement designation for generation of addresses of pixels adjoining a pixel to which attention is being paid, said index register being constituted by a plurality of up/down counters interconnected in a cascade configuration to receive carry signals;   a shared memory into which image data on said desired portions is successively written by said address processor; and   an operational processor for effecting data processing with respect to said image data on said desired portions.   
     
     
       29. An image processor according to claim 28, wherein said address processor further comprises a buffer memory operatively interconnected between said image memory and said shared memory, said buffer memory being suitable for performing processes of receiving said image data from said image memory, and said address register being coupled to said buffer memory for effecting address control of said buffer memory and conducting read and write operations on said buffer memory after performing said arithmetic operations. 
     
     
       30. An image processor according to claim 29, wherein said buffer memory and said address register are each controllable by said address processor simultaneously complete one of said processes and said operations, respectively. 
     
     
       31. An image processor according to claim 30, further comprising: an instruction word memory discrete from said image memory for storing the processing program separately from said image data; and   a mechanism suitable for reading out a subsequent instruction from said instruction word memory while operating upon image data in accordance with a preceding instruction.