Analysis process of a line transfer photosensitive device and operating device of such a process

Abstract

The present invention concerns an analysis process of a line transfer photosensitive device. The charge-signal and the charge noise transfers from the columns towards the memory have the same duration and are made by using a same training charge, stored in memory, that must be at least sufficient to allow to pass in high inversion at the beginning of the transfer from the columns towards the memory. The transfers of the charge-signal and the charge-noise from the memory towards the read-out register or the drain have the same duration and are made by using training charges at least sufficient to allow to pass in high inversion at the beginning of the transfer. These training charges are read with the charge-signal or collected with the charge-noise.

We claim: 
     
       1. Analysis process of a line transfer photosensitive device, this device comprising a photosensitive zone of M lines of N photosensitive points, wherein charge signals (Q S ) are produced proportional to received illumination of an image; the photosensitive points of the different lines being connected in parallel by conducting columns to a memory having N intermediary capacitances, said memory ensuring the transfer towards a read-out register of the charge-signal (Q S ) of a single line and ensuring the transfer towards a drain of charge-noise (Q B ) present on the columns prior to the intake of the charge-signal wherein the analysis of each line of the photosensitive zone comprises the following steps: transfer of the charge-signal (Q S ) towards the memory, by superimposing on the charge-signal at least a first training charge (Q O ), this first training charge (Q O ) being stored in the intermediary capacitances and transferred on the columns prior to the intake of the charge-signal and being sufficient to obtain in the columns, at the beginning of the transfer of the columns towards the intermediary capacitances a charge to be positioned in the high inclination zone of the characteristic Q(t) of the columns.   transfer of a second training charge (Q 1 ), superimposed on the charge-signal (Q S ) towards the read-out register, this second training charge (Q 1 ) being read with the charge-signal (Q S ) and being sufficient to obtain in the intermediary capacitances at the beginning of the transfer a charge to be positioned in the high inclination zone of the characteristic Q(t) of the intermediary capacitances.   
     
     
       2. Process according to claim 1, characterized in that the evacuation of the charge-nose (Q B ) present on the columns prior to the intake of the charge-signal comprises the following steps: transfer of the charge-noise (Q B ) from the columns towards the memory by superimposing on it the same first training charge (Q O ) as for the charge-signal, the transfer having the same duration (T L ) as the transfer of the charge-signal of the column towards the intermediary capacitances and the first training charge (Q O ) still being stored in the intermediary capacitances and periodically transferred on the columns;   transfer of the charge-noise (Q B ) of the memory towards the drain by superimposing on it a third training charge (Q 2 ) being sufficient to obtain in the intermediary capacitances at the beginning of the transfer a charge to be positioned in the high inclination zone of the characteristic Q(t) of the intermediary capacitances, this transfer having the same duration (t 1 ) as the transfer of the charge-signal (Q S ) of the intermediary capacitances towards the read-out register and this third training charge being evacuated with the charge-noise towards the drain.   
     
     
       3. Process according to claim 1, wherein the first training charge (Q O ) is significant with respect to the maximum value of the charge-signal (Q S  max). 
     
     
       4. Process according to claim 1, wherein the second training charge (Q 1 ) is low with respect to the maximum value of the charge signal (Q S  max). 
     
     
       5. Process according to claim 1, wherein the second training charge (Q 1 ) is obtained by injecting permanently this charge quantity into the read-out register and by transferring it into the memory prior to the intake of the charge-signal. 
     
     
       6. Process according to claim 1, wherein the second training charge (Q 1 ) is obtained by injection at the level of the intermediary capacitance (C 2 ) that comprises the memory. 
     
     
       7. Process according to claim 1, wherein the second training charge (Q 1 ) is obtained by illuminating by a uniform lighting of the photosensitive zone so as to generate permanently a charge that is superimposed on the charge-signal. 
     
     
       8. Process according to claim 7, wherein, in the case of a photosensitive zone covered by colored filters, the uniform lighting is realized in a wave length such that the transmission of the colored filters is equivalent, whatever the filter. 
     
     
       9. Process according to claim 2, wherein the third training charge (Q 2 ) is introduced into the memory from the drain. 
     
     
       10. Process according to claim 2, wherein the third training charge (Q 2 ) is obtained by injecting in series during the line time this charge quantity into a charge transfer shift register of series input and parallel outputs positioned parallel-wise to the line memory and by transferring it from the register towards the line memory. 
     
     
       11. Process according to claim 10, wherein the charge transfer shift register is positioned at the end of the columns of the photosensitive zone on the side opposite the line memory, the charge transfer towards the line memory being realized by the intermediary of the columns. 
     
     
       12. Process according to claim 10, wherein the charge transfer shift register is adjacent to the read-out register, which is constituted by a volume transfer type register, the two registers being controlled by identical control phases (φ 1 , φ 2 ) and communicating at the level of one of the phases (φ 2 ), by the intermediary of a gate of passage (φ p ), the third training charge (Q 2 ) being injected in the read-out register and the second training charge (Q 1 ) in the shift register. 
     
     
       13. Process according to claim 12, wherein the charge transfer shift register is a volume transfer type shift register with an impurity implantation quantity lower than that of the read-out register. 
     
     
       14. Process according to claim 12, wherein the second and third training charges (Q 1 , Q 2 ) are obtained by separation of a single charge (Q e ) injected in the input stage common to the charge transfer shift register and to the read-out register. 
     
     
       15. Process according to claim 12, wherein the second and third training charges (Q 1 , Q 2 ) are separately injected by different input stages in the charge transfer shift register and in the read-out register. 
     
     
       16. Process according to claim 2, wherein the second and third training charges (Q 1 , Q 2 ) are obtained by injecting in series during line time a charge quantity into the read-out register that comprises a number of stages allowing to store successively for one stage of line memory, two identical charge quantities corresponding to the second and third training charges. 
     
     
       17. Process according to claim 2, wherein the second and third training charges are obtained by injecting in series, during the line time, a charge quantity into the read-out register constituted by a series-parallel shift register comprising at least two storage electrodes for one line memory stage, one of the storage electrodes not communicating with the line memory being constituted by two parts of the electrodes so as to separate the injected charge into two charges, the control phase (φ, φ 1 , φ 2 )applied on the different electrodes being selected in such a way as to be able to separately transfer the two charges towards the line memory. 
     
     
       18. Process according to claim 10, wherein the second and third training charges are injected in charge transfer shift registers comprising a number of stages superior to the number of stages of the line memory. 
     
     
       19. A method for an analysis process of a photosensitive device, comprising a photosensitive zone of M lines of N photosensitive points, wherein charge signals (Q S ) are produced proportional to received illumination of an image; the photosensitive points of the different lines being connected in parallel by conducting columns to a memory having N intermediary capacitances, said memory ensuring the transfer via a switchover means towards a read-out register of the charge-signal (Q S ) of a single line and ensuring the transfer via the switchover means towards a drain of charge-noise (Q B ) present on the columns prior to the intake of the charge-signal wherein the analysis of each line of the photosensitive zone comprises the following steps: connect the line memory to the drain via the switchover means,   transfer the noise signal (Q B ) to the drain,   connect the line memory to the read-out register via the switchover means,   transfer of the charge-signal (Q S ) towards the memory, by superimposing on the charge-signal at least a first training charge (Q O ) being stored in the intermediary capacitances and transferred on the columns prior to the intake of the charge-signal and being sufficient to obtain in the columns, at the beginning of the transfer of the columns towards the intermediary capacitances a charge to be positioned in the high inclination zone of the characteristic Q(t) of the columns,   transfer of a second training charge (Q 1 ) superimposed on the charge-signal (Q S ) towards the read-out register, this second training charge (Q 1 ) being read with the charge-signal (Q S ) and being sufficient to obtain in the intermediary capacitances at the beginning of the transfer a charge to be positioned in the high inclination zone of the characteristic Q(t) of the intermediary capacitances.   
     
     
       20. Device according to claim 19, wherein the line memory is a double stage memory of which the switchover means are constituted by a series of capacitances, the access to each capacitance being controlled by three gates, a gate that allows the intake of the charges issuing from the intermediary capacitances and which retains the first training charge and two gates that allow the transfer of the charges towards the drain or towards the read-out register. 
     
     
       21. Process according to claim 4, wherein the second training charge (Q1) is equal to Qs max/10. 
     
     
       22. Process according to claim 2, wherein the first training charge (Q O ) is significant with respect to the maximum value of the charge-signal (Q S  max). 
     
     
       23. Process according to claim 16, wherein the second and third training charges are injected into charge transfer shift registers comprising a number of stages superior to the number of stages of the line memory. 
     
     
       24. Process according to claim 17, wherein the second and third training charges are injected into charge transfer shift registers comprising a number of stages superior to the number of stages of the line memory. 
     
     
       25. A method for an analysis process of a photosensitive device, comprising a photosensitive zone of M lines of N photosensitive points, wherein charge signals (Q S ) are produced proportional to received illumination of an image; the photosensitive points of the different lines being connected in parallel by conducting columns to a memory having N intermediary capacitances, said memory ensuring the transfer via a switchover means towards a read-out register of the charge-signal (Q S ) of a single line and ensuring the transfer via the switchover means towards a drain of charge-noise (Q B ) present on the columns prior to the intake of the charge-signal wherein the analysis of each line of the photosensitive zone comprises the following steps: connect the line memory to the drain via the switchover means,   transfer the noise signal (Q B ) to the drain,   connect the line memory to the read-out register via the switchover means,   transfer of the charge-signal (Q S ) towards the memory, by superimposing on the charge-signal at least a first training charge (Q O ) being stored in the intermediary capacitances and transferred on the columns prior to the intake of the charge-signal and being sufficient to obtain in the columns, at the beginning of the transfer of the columns towards the intermediary capacitances a charge to be positioned in the high inclination zone of the characteristic Q(t) of the columns,   transfer of a second training charge (Q 1 ) superimposed on the charge-signal (Q S ) towards the read-out register, this second training charge (Q 1 ) being read with the charge-signal (Q S ) and being sufficient to obtain in the intermediary capacitances at the beginning of the transfer a charge to be positioned in the high inclination zone of the characteristic Q(t) of the intermediary capacitances, and wherein the evacuation of the charge-noise (Q B ) present on the columns prior to the intake of the charge-signal comprises the following steps:   transfer of the charge-noise (Q B ) from the columns towards the memory by superimposing on it the charge-signal, the transfer having the same duration (T L ) as the transfer of the charge-signal of the column towards the intermediary capacitances and the first training charge (Q O ) still being stored in the intermediary capacitances and periodically transferred on the columns;   transfer of the charge-noise (Q B ) of the memory towards the drain by superimposing on it a third training charge (Q 2 ) being sufficient to obtain in the intermediary capacitances at the beginning of the transfer a charge to be positioned in the high inclination zone of the Q(t) of the intermediary capacitances, this transfer having the same duration (t 1 ) as the transfer of the charge-signal (Q S ) of the intermediary capacitances towards the read-out register and this third training charge being evacuated with the charge-noise towards the drain.   
     
     
       26. Device according to claim 25, wherein the line memory is a double stage memory of which the switchover means are constituted by a series of capacitances, the access to each capacitance being controlled by three gates, a gate that allows the intake of the charges issuing from the intermediary capacitances and which retains the first training charge and two gates that allow the transfer of the charges towards the drain or towards the read-out register.