System for high accuracy remote decoding

Abstract

An encode-decoder system for generating highly accurate, coinciding synchronizing signals at each of plural separated locations; for example, a system generating start signals for a seismic data acquisition system. The system transmits psuedo random code data over selected communication link to a respective position decoder which samples the incoming code and compares it with a standard code. If there can be established a predetermined number of successive code matches, an output start signal is enabled when the code match count first peaks and then decreases.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows: 
     
       1. A method for reliably producing accurate start signals at remotely disposed locations, comprising the steps of: selecting a time zero delay and initiating transmission from a first location of a selected data code of known duration less than said delay;   producing a first start signal at said first location upon expiration of said time zero delay;   receiving said selected data code at a second location and storing serial code bits for said duration;   comparing said selected data code with a standard code stored as serial code bits by comparing successive bits for each of plural groups of bits simultaneously to derive a serial code match count;   detecting first decrease in code match count indicative of complete code reception for the known duration; and   producing a second start signal at said second location upon decrease of code match count that is in general coincidence with said first start signal.   
     
     
       2. A method as set forth in claim 2 wherein said step of comparing comprises: serially dividing the received stored data bits into a plurality of successive groups of data code bits and simultaneously comparing with a plurality of successive groups of standard code bits;   gating out code bit comparison outputs for each successive bit of each group;   summing the successive comparison outputs for all groups; and   accumulating a count of the successive sums until the count does not advance indicating all code bits properly compared.   
     
     
       3. Apparatus for producing highly accurate start signals at remotely disposed locations, comprising: encoder means for selecting a time zero delay and initiating transmission from a first location of a selected data code of known duration less than said delay;   means for producing a first start signal at said first location upon expiration of said time zero delay;   means for receiving the selected data code at a second location and storing serial code bits for said duration;   means for comparing said selected data code with a standard code stored as serial code bits by comparing successive bits for each of plural groups of bits simultaneously to derive a serial code match count output;   means for detecting first decrease in match count output indicative of complete code reception for the known duration; and   means for producing a second start signal at said second location upon match count output decrease that is in general coincidence with said first start signal.   
     
     
       4. Apparatus as set forth in claim 3 wherein said encoder means comprises: switch means providing a selected count output indicative of selected delay;   counter means counting timing pulses at an incremental time rate to produce a timing pulse count output;   comparator means comparing said selected count output and timing pulse count output to produce a count equal output to actuate said means for producing.   
     
     
       5. Apparatus as set forth in claim 4 wherein said encoder means further comprises: switch means for selecting a data code of a predetermined number of serial code bits; and   means for transmitting said selected data code serial bits.   
     
     
       6. Apparatus as set forth in claim 3 wherein said means for receiving and storing comprises: plural shift register means connected to receive serial loading of said data code bits for storage, with each shift register means containing a selected different portion of the total data code bits; and   means including latch means for selectively recirculating stored data code bits of each shift register means to generate plural successive compare outputs.   
     
     
       7. Apparatus as set forth in claim 6 wherein said means for comparing comprises: plural shift register means connected to receive serial loading of said standard code bits for storage, with each shift register means containing a selected different portion of the total standard code bits;   means including latch means for selectively recirculating stored standard code bits of each shift register means to generate plural successive compare outputs; and   gate comparison means receiving input of compare outputs for each respective pairs of data code and standard code shift register means to generate respective code match count outputs.   
     
     
       8. Apparatus as set forth in claim 7 wherein: each of said shift register means is a dual operation shift register wherein opposite phase clocks control simultaneous shift control of respective halves of the total bit capacity.   
     
     
       9. Apparatus as set forth in claim 8 wherein: each of said shift register means is a dual 512 bit shift register processing two 256 bit data groups simultaneously.   
     
     
       10. Apparatus as set forth in claim 3 wherein said means for detecting comprises: means for summing the successive match count output;   means for counting a selected multiple of successive match count outputs to accumulate a code match total; and   means generating an output in response to first detection of a decrease in said code match total.   
     
     
       11. Apparatus as set forth in claim 10 which further includes: switch means for selected a threshold input indicative of code match total; and   comparator means receiving said threshold input to produce a code match enabling output to said means for producing.   
     
     
       12. Apparatus for generating an accurately timed sychronizing control signal comprising: means inputting a digital data code of selected number of code bits and duration;   means inputting a digital standard code of said selected number of code bits and duration;   a data shift register receiving serial input of said data code bits;   a standard shift register retaining stored serial input of said standard code bits;   first means controlling shift of said data code bits through the data shift register;   second means controlling shift of said standard code bits through the standard shift register;   gate means receiving input of said data code bits and standard code bits and generating a coincidence output for each code match;   means for counting said coincidence outputs to store a successive code match count;   means comparing current code match count with previous code match count to generate a trigger pulse upon count decrease; and   circuit means responsive to said trigger pulse to generate said synchronizing control signal.