Digital multifrequency signal receiver

Abstract

A digital multifrequency receiver circuit of the type employed between telephone system central offices, arranged to provide a faster response to received signals by processing the received signal tones digitally. The faster response resulting from the elimination of automatic gain control circuits and the use of a fixed gain amplifier used only when the received signal is below an acceptable level and the provision of a variable threshold to the individual frequency comparator circuits.

What is claimed is: 
     
       1. A digital detector device for telephone band multifrequency signalling comprising: a digital filter having an input to which the signal source is connected and an output,   a level shifter amplifier having an input connected to the output of said digital filter and an output,   a plurality of individual frequency detectors each having a first and a second input and an output,   said frequency detectors each comprising;   a band pass filter connected to the output of said level shifter,   a digital integrator and,   a comparator connected in series,   a guard path circuit comprising an integrator, a digital multiplier and an adder circuit, in series, an input to said integrator connected to the output of said level shifter, and an output connected to the second input of each of said comparator circuits,   said output comprising a variable reference level for said signal comparison in said comparator circuits.   
     
     
       2. An arrangement as claimed in claim 1, characterized in that said level shifter comprises; an amplifier,   a level detector and,   a two way switch,   said level detector operatively connected to control said switch to connect said amplifier into the signal path upon detecting an incoming signal below a designated level.   
     
     
       3. An arrangement as claimed in claim 2, characterized in that said level detector is operated to disconnect said amplifier from said signal path upon detecting an incoming signal above a second designated level. 
     
     
       4. An arrangement as claimed in claim 1, characterized in that said band pass filters are of an order lower than the 4th order. 
     
     
       5. An arrangement as claimed in claim 2, characterized in that said band pass filters are of an order lower than the 4th order. 
     
     
       6. An arrangement as claimed in claim 3, characterized in that said band pass filters are of an order lower than the 4th order. 
     
     
       7. An arrangement as claimed in claim 1, characterized in that said digital filter is comprised of a microprocessor. 
     
     
       8. An arrangement as claimed in claim 4, characterized in that said digital filter is comprised of a microprocessor. 
     
     
       9. An arrangement as claimed in claim 1, characterized in that said band pass filter is comprised of a microprocessor. 
     
     
       10. An arrangement as claimed in claim 7, characterized in that said band pass filter is comprised of a microprocessor. 
     
     
       11. An arrangement as claimed in claim 1, characterized in that said multiplier and adder circuits are comprised of a microprocessor. 
     
     
       12. An arrangement as claimed in claim 9, characterized in that said multiplier and adder circuits are comprised of a microprocessor.