Method of manufacture of a semiconductor device

Abstract

This invention discloses a semiconductor device, and method of manufacturing such device, which provides a high degree of moistureproofing, provides a high production yield, and in which defective elements can be replaced by the use of fuses. A circuit test of the device is conducted while at least part of each of a fuse and a bonding pad is exposed through a first passivation film covering a semiconductor substrate on which circuit elements such as MISFETs and capacitors are formed, and any defective elements are replaced by the use of fuses. Contamination of and damage to the elements during the test can thus be prevented. Thereafter, a second passivation film is formed so as to cover all the essential portions of the fuses and bonding pads. The exposure of cracks in the fuses and bonding pads is thus prevented, and the invasion of moisture, etc., into the lower layers below the fuses and bonding pads is also prevented, thereby improving the moistureproofing and reliability of the device.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device provided with a plurality of fuses formed on a semiconductor substrate, said semiconductor device also including at least one bonding pad over said substrate, comprising the steps of: (a) forming a first passivation film over said semiconductor substrate except for at least part of each of said fuses and except for at least part of each of said at least one bonding pad;   (b) brining a first group of said fuses into a first state and a second group of said fuses different from said first group of said fuses into a second state, the electrical resistance of said fuses in said first state being much greater than that of those in said second state, the difference between said electrical resistances being provided by said part of each of said fuses not covered by said first passivation film; and   (c) forming a second passivation film over said semiconductor substrate so as to cover at least said part of each of the said fuses not covered by said first passivation film.   
     
     
       2. The method of manufacturing a semiconductor device as defined in claim 1, wherein said first state is established by cutting the portions of said first group of said fuses not covered by said first passivation film. 
     
     
       3. The method of manufacturing a semiconductor device, as defined in claim 1, wherein said fuses are made of polysilicon. 
     
     
       4. The method of manufacturing a semiconductor device as defined in claim 3, wherein the polysilicon of the fuses has been doped with impurities so as to reduce the resistance thereof. 
     
     
       5. The method of manufacturing a semiconductor device as defined in claim 1, wherein said second passivation film leaves exposed a portion of each of said bonding pads. 
     
     
       6. The method of manufacturing a semiconductor device as defined in claim 5, wherein the first passivation film is a two-layered structure of an SiO 2  film having a phosphosilicate glass film, formed by chemical vapor deposition, thereover. 
     
     
       7. The method of manufacturing a semiconductor device as defined in claim 1, wherein the first passivation film is a passivation film formed by chemical vapor deposition. 
     
     
       8. The method of manufacturing a semiconductor device as defined in claim 7, wherein the first passivation film is a phosphosilicate glass film formed by chemical vapor deposition. 
     
     
       9. The method of manufacturing a semiconductor device as defined in claim 7, wherein the second passivation film is formed by chemical vapor deposition. 
     
     
       10. The method of manufacturing a semiconductor device as defined in claim 9, wherein the second passivation film is a film of SiO 2  or silicon nitride, formed by chemical vapor deposition. 
     
     
       11. The method of manufacturing a semiconductor device as defined in claim 1, wherein the second passivation film is formed by chemical vapor deposition. 
     
     
       12. The method of manufacturing a semiconductor device as defined in claim 1, wherein said fuses comprise a silicide of a metal with a high melting point. 
     
     
       13. A method of manufacturing a semiconductor device comprising the steps of: (a) forming a plurlity of fuses and a plurality of elements on a semiconductor substrate;   (b) forming a plurality of bonding pads and wiring on said semiconductor substrate;   (c) forming a first passivation film over said semiconductor substrate except for at least part of each of said fuses and except for at least part of each of the bonding pads;   (d) bringing a first group of said fuses into a first state and a second group of said fuses different from said first group of said fuses into a second state, the electrical resistance of said fuses in said first state being much greater than that of those in said second state, the difference between said electrical resistances being provided by said part of each of said fuses not covered by said first passivation film; and   (e) forming a second passivation film over said semiconductor substrate so as to cover said part of each of said fuses not covered by said first passivation film.   
     
     
       14. The method of manufacturing a semiconductor device as defined in claim 13, wherein said elements include MIS devices, each of said MIS devices consisting of an electrode formed on said semiconductor substrate with an insulating film interposed therebetween, said fuses and said electrodes being made of the same material. 
     
     
       15. The method of manufacturing a semiconductor device as defined in claim 14, wherein said an electrode and said fuses are made of polysilicon. 
     
     
       16. The method of manufacturing a semiconductor device as defined in claim 15, wherein said MIS devices includes MIS capacitors. 
     
     
       17. The method of manfacturing a semiconductor device as defined in claim 13, wherein each of said bonding pads is formed as an integral member. 
     
     
       18. The method of manfacturing a semiconductor device as defined in claim 13, wherein each of said bonding pads are formed of first and second portions formed independently of each other, said first and second portions being electrically connected to each other by said wiring. 
     
     
       19. The method of manufacturing a semiconductor device as defined in claim 13, wherein a portion of each of said bonding pads includes cracks, and wherein the step of forming the second passivation film includes covering said cracks by said second passivation layer. 
     
     
       20. The method of manufacturing a semiconductor device as defined in claim 13, wherein said step (d) comprises the following sub-steps: (f) bringing a probe for testing for the presence of defective elements into contact with said portions of said part of said bonding pads not covered by the first passivation film;   (g) conducting said test; and   (h) bringing said fuses into said first or second state on the basis of the results of said test.   
     
     
       21. The method of manufacturing a semiconductor device as defined in claim 13, which further comprises the following steps: (i) forming an inter-layer insulating film over said semiconductor substrate so as to cover said fuses and said elements, after said step (a) and before said step (b); and   (j) removing at least part of said inter-layer insulating film over each of said fuses.   
     
     
       22. The method of manufacturing a semiconductor device as defined in claim 21, wherein the part of each of said fuses not covered by said inter-layer insulating film is wider than the part of each of said fuses not covered by said first passivation film. 
     
     
       23. The method of manufacturing a semiconductor device as defined in claim 22, wherein contact holes for connecting said elements to said wiring are formed by removing said inter-layer insulating film in said step (j). 
     
     
       24. The method of manfacturing a semiconductor device as defined in claim 13, wherein said second passivation film leaves exposed a portion of each of said bonding pads. 
     
     
       25. Th method of manufacturing a semiconductor device as defined in claim 13, wherein the first passivation film is a passivation film formed by chemical vapor deposition. 
     
     
       26. The method of manufacturing a semiconductor device as defined in claim 25, wherein the second passivation film is formed by chemical vapor deposition. 
     
     
       27. The method of manufacturing a semiconductor device as defined in claim 26, wherein said elements include MISFETs, said MISFETs each have a gate electrode, and wherein the gate electrodes of the MISFETs comprise a layer of polycrystalline silicon having a silicide layer thereon. 
     
     
       28. The method of manufacturing a semiconductor device as defined in claim 27, wherein said silicide layer is a layer of a silicide of a metal with a high melting point. 
     
     
       29. The method of manufacturing a semiconductor device as defined in claim 28, wherein said metal with a high melting point is selected from the group consisting of Mo, W, Ti and Ta. 
     
     
       30. The method of manufacturing a semiconductor device as defined in claim 28, wherein the elements further include capacitors, with each capacitor including a polycrystalline silicon electrode layer formed over the semiconductor substrate. 
     
     
       31. The method of manufacturing a semiconductor device as defined in claim 13, wherein said elements include MISFETs, said MISFETs each have a gate electrode, and wherein the gate electrodes of the MISFETs comprise a layer of polycrystalline silicon having a silicide layer thereon. 
     
     
       32. The method of manufacturing a semiconductor device as defined in claim 31, wherein the elements further include capacitors, with each capacitor including a polycrystalline silicon electrode layer formed on the semiconductor substrate. 
     
     
       33. The method of manufacturing a semiconductor device as defined in claim 13, wherein said elements include electrodes formed on the semiconductor substrate, the electrodes and fuses being formed from the same layer of conductive material. 
     
     
       34. The method of manufacturing a semiconductor device as defined in claim 33, wherein said electrodes are electrodes of MIS elements. 
     
     
       35. The method of manufacturing a semiconductor device as defined in claim 34, wherein said electrodes are electrodes of capacitors. 
     
     
       36. The method of manufacturing a semiconductor device as defined in claim 35, wherein said same layer of conductive material is made of polycrystalline silicon. 
     
     
       37. A method of manufacturing a semiconductor device provided with MISFETs and capacitors, comprising: (a) forming fuses and said capacitors on a semiconductor substrate, each of said capacitors consisting of electrodes formed on said semiconductor substrate with an insulating film interposed therebetween, said fuses being made of the same material as that of said electrodes;   (b) forming said MISFETs on said semiconductor substrate, each of said MISFETs having a gate electrode formed on said semiconductor substrate with an insulating film interposed therebetween;   (c) forming an inter-layer insulating film covering said fuses, said capacitors and said MISFETs, on said semiconductor substrate;   (d) forming wiring and contact holes for connecting said capacitors to said MISFETs;   (e) forming bonding pads and wirings on said inter-layer insulating film;   (f) forming a first passivation film over said semiconductor substrate except for at least part of each of said fuses and a part of each of said bonding pads;   (g) bringing a first group of said fuses into a first state and a second group of said fuses different from said first group of said fuses into a second state, the electrical resistance of said fuses in said first state being much greater than that of said fuses in said second state, the difference between said electrical resistances being provided by part of each of said fuses not covered by said first passivation film; and   (h) forming a second passivation film over said semiconductor substrate so as to cover said part of each of said fuses not covered by said first passivation film.   
     
     
       38. The method of producing a semiconductor device as defined in claim 37, wherein said step (b) of forming said MISFETs includes a sub-step of forming a conductor layer on at least portions of each of said fuses, and wherein said inter-layer insulating layer is formed to expose at least portions of said conductor layer on each of said fuses, and comprises the step of: (i) removing the portions of said conductor layer on the fuses not covered by said inter-layer insulating film, after said step (e), said conductor layer being of the same material as that of said gate electrodes.   
     
     
       39. The method of producing a semiconductor device as defined in claim 38, wherein said conductor layer is formed on at least portions of each of said fuses, and also on said semiconductor substrate with an insulating film interposed therebetween to form said gate electrode of each of said MISFETs. 
     
     
       40. The method of producing a semiconductor device as defined in claim 38, wherein said conductor layer comprises a first film of polysilicon covered with a second film of a silicide of a metal with a high melting point. 
     
     
       41. The method of manufacturing a semiconductor device as defined in claim 37, wherein said gate electrode of each of the MISFETs comprises a polycrystalline silicon layer having a layer of a silicide thereon. 
     
     
       42. The method of manufacturing a semiconductor device as defined in claim 41, wherein said silicide is a silicide of a metal with a high melting point. 
     
     
       43. The method of manufacturing a semiconductor device as defined in claim 42, wherein said electrodes, of said capacitors, formed on said semiconductor substrate are comprised of polycrystalline silicon. 
     
     
       44. The method of manufacturing a semiconductor device as defined in claim 27, wherein said electrodes, of said capacitors, formed on said semiconductor substrate are comprised of polycrystalline silicon. 
     
     
       45. The method of manufacturing a semiconductor device as defined in claim 37, wherein said semiconductor device is a dynamic random access memory. 
     
     
       46. The method of manufacturing a semiconductor device as defined in claim 1, wherein said semiconductor substrate also has semiconductor elements thereon, the semiconductor elements including electrodes of the same layer of conductive material as said plurality of fuses, with said first passivation film being formed over the electrodes. 
     
     
       47. A method of producing a semiconductor device, comprising the steps of: (a) forming a thick insulating film over a main surface of a semiconductor substrate so as to divide said main surface into a plurality of regions in which elements will be formed;   (b) forming elements mainly located in said plurality of regions separated by said thick insulating film;   (c) forming fuses on said thick insulating film;   (d) forming bonding pads over the main surface of the semiconductor substrate;   (e) forming a first passivation film so as to cover said semiconductor substrate except for at least part of each of said fuses and except for at least part of the bonding pads formed over the main surface of the semiconductor substrate;   (f) bringing a first group of said fuses into a first state and a second group of said fuses different from said first group of said fuses into a second state, the electrical resistance of said first group of said fuses being much greater than that of said fuses in said second state; and   (g) forming a second passivation film covering at least said part of each of said fuses not covered by said first passivation film.   
     
     
       48. The method of manufacturing a semiconductor device as defined in claim 47, wherein said second passivation film leaves exposed a portion of each of said bonding pads.