Pockels cell driver

Abstract

A Pockels cell driver using a microwave triode which transfers charge from a high voltage source to a Pockels cell via a storage capacitor. The microwave tube is controlled, through its grid voltage, by two pulse amplifiers each having a plurality of tandem field effect transistor (FET) stages so as to increase the voltage across the cell in two steps having a selected delay therebetween. The driver is especially useful for seeding and extracting output pulses from a regenerative laser amplifier having the Pockels cell within its cavity. The driver may be used to operate a Pockels cell as a switchout or shutter to select a single pulse from a pulse laser such as a mode-locked Q-switched laser.

We claim: 
     
       1. In a Pockels cell driver circuit wherein a Pockels cell is charged via a vacuum tube having a grid to increase the voltage across the cell in a plurality of steps having a selected delay between each of said steps, the improvement comprising a plurality of pulse amplifiers, each of said amplifiers having an input for a separate one of a plurality of trigger pulses having said selected delay between of said trigger pulses, and each of said amplifiers having an output connected to the grid of said tube for applying amplified pulses corresponding to said trigger pulses which are applied to the input thereof to enable said cell to charge to each of said voltage steps. 
     
     
       2. The improvement according to claim 1 wherein each of said amplifiers has connected to said output thereof means for controlling the charge transferred to said grid during each of said pulses. 
     
     
       3. The improvement according to claim 2 wherein each of said amplifiers has an output circuit including a source of voltage for supplying said charge, and a coupling capacitor connected to said grid, at least one of the magnitude of said voltage from said source and the capacitance of said capacitor being variable. 
     
     
       4. The improvement according to claim 2 wherein said output circuit comprises a FET having gate, source and drain electrodes means for applying the pulse amplified and said amplified to said gate, said voltage source being connected in series with said source and drain electrodes and said coupling capacitor being connected between one of said source and drain and said grid. 
     
     
       5. The improvement according to claim 1 wherein each of said pulse amplifiers comprises a plurality of tandem connected FET current amplifier stages. 
     
     
       6. The improvement according to claim 5 wherein one of said stages is the output stage of said amplifier and includes an output FET having gate, source and drain electrodes, a pulse transformer coupling the one of said FET stages preceding said output stage to the gate of said output stage FET, a source of voltage, a resistor, said voltage source and said resistor being connected in series with said source and drain electrodes of said output FET, and a coupling capacitor connected between one of said source and drain electrodes of said output FET and said grid. 
     
     
       7. The improvements according to claim 6 wherein said pulse transformer has a primary winding and a secondary winding, said secondary winding being connected between said gate of said output FET and one of said source and drain thereof, said preceding FET also having gate source and drain electrodes, said primary being connected in series with a second source of voltage and said drain and source of said preceding FET, and a capacitor connected between one end of said primary winding and a point of reference potential for said second source of voltage. 
     
     
       8. The improvement according to claim 5 further comprising a bi-polar transistor current amplifier stage in tandem between two of said plurality of FET amplifier stages. 
     
     
       9. The improvement according to claim 8 wherein said by-polar transistor stage includes a transistor having a base and an emitter and a collector, one of said base and emitter being connected to the gate of the one of said FET stages intermediate to the stages thereof which are connected to said input and output of said amplifier, and said base being connected to one of the drain and source and of the FET stage immediately preceding said one intermediate FET stage. 
     
     
       10. The improvement according to claim 1 further comprising a further source of voltage connected to said grid and polarized to maintain said tube nonconductive in the absence of a pulse from the output of any of said plurality of amplifiers.