Semiconductor memory device

Abstract

A semiconductor memory device including at least two groups, each of said groups including a plurality of memory cell array blocks. The number of the memory cell array blocks which are activated in one group is made different from the number of memory cell array blocks which are activated in another group by providing a sequential circuit, thus reducing the maximum power consumption.

We claim: 
     
       1. A semiconductor memory device comprising: at least two groups each including a plurality of memory cell array blocks;   each of said memory cell array blocks including a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells each being connected between respective ones of said bit line pairs and word lines;   switching means connected between respective bit line pairs of adjoining pairs of said memory cell array blocks of each said group, for selectively splitting and connecting said respective bit line pairs of said adjoining pairs of memory cell array blocks of the respective group;   column decoder means operatively connected to the bit line pairs of a first of said memory cell array blocks of each said group, for selecting a bit line pair therefrom to read data from a selected memory cell in the respective group;   a word decoder for simultaneously selecting one of said word lines in one of said memory cell array blocks in a first one of said groups and one of said word lines in one of said memory cell array blocks in a second of said groups, in such a way that the distance between a first respective part of said column decoder means and the memory cell array block with the respective selected word line of said first group is different from the distance between a second respective part of said column decoder means and the memory cell array block with the selected word line of said second group; and   a switching control circuit for controlling said switching means so as to selectively connect the bit line pairs of each said memory cell array block having said selected word line that has the greater value of said distance and in another of the memory cell array blocks of the same group that is located between said memory cell array block of said greater value of said distance and said column decoder.   
     
     
       2. A semiconductor memory device as set forth in claim 1, further comprising a plurality of sense amplifiers, each for amplifying the potential difference between the bit line pairs of at least one respective one of said memory cell array blocks, wherein: said switching control circuit comprises a sequential circuit;   said switching means comprises a plurality of groups of transfer gate transistors, each group of said transfer gate transistors being connected along the respective bit line pairs between a respective one of said memory cell array blocks and a respective one of said plurality of sense amplifiers; and   said sequential circuit is operatively connected to said transfer gate transistors to control the number of groups of said transfer gate transistors opened by said sequential circuit in said first group of memory cell array blocks to be different from the number of groups of said transfer gate transistors opened by said sequential circuit in said second group of memory cell array blocks.   
     
     
       3. A semiconductor memory device as set forth in claim 1, further comprising a plurality of sense amplifiers, each for amplifying the potential difference between the bit line pairs of at least one respective one of said memory cell array blocks, said switching control circuit comprising a sequential circuit, operatively connected to said sense amplifiers, for controlling said sense amplifiers in such a way that the number of activated sense amplifiers in said first group is different from the number of activated sense amplifiers in said second group. 
     
     
       4. The device of claim 3, comprising one of said plurality of sense amplifiers for each of said memory cell array blocks, said switching means having respective parts connected along the respective bit line pairs in between the two pluralities of sense amplifiers of the respective adjoining pair of memory cell array blocks of each said group, and said switching control circuit including a selection circuit for alternately operating said respective parts of said switching means in said two groups. 
     
     
       5. The device of claim 3, comprising one of said pluralities of sense amplifiers for each said memory cell array block, wherein said switching means has a respective part connected along the respective bit lines between the respective two pluralities of sense amplifiers of each adjoining pair of said memory cell array blocks. 
     
     
       6. A semiconductor memory device as set forth in claim 3, wherein said switching means comprises a plurality of pairs of transfer gate transistors, each group of said transfer gate transistors being connected between respective ones of said bit line pairs of said adjoining pairs of memory cell array blocks. 
     
     
       7. A semiconductor memory device as set forth in claim 6, wherein said switching control circuit further comprises a selection circuit operatively connected to said plurality of groups of transfer gate transistors, for controlling each said group of transfer gate transistors in such a way that the number of groups of said transfer gate transistors opened by said selection circuit in said first group of memory cell array blocks is different from the number of groups of said transfer gate transistors opened by said selection circuit in said second group of memory cell array blocks. 
     
     
       8. The device of claim 3, comprising one of said pluralities of sensing amplifiers for each adjoining pair of said memory cell array blocks, and a respective part of said switching means for each said memory cell array block, wherein each said plurality of sensing amplifiers is connected along the respective bit line pairs in between the respective pluralities of sensing amplifiers of the respective adjoining pair of memory cell array blocks. 
     
     
       9. The device of claim 8, said column decoder means comprising two column decoders, one for each said group, each said column decoder being connected to the bit line pairs of a respective one of the memory cell array blocks. 
     
     
       10. The device of claim 3, said switching means including a respective part corresponding to each said memory cell array block, wherein there is one of said pluralities of sense amplifiers for each adjoining pair of said memory cell array blocks, and wherein each said plurality of sense amplifiers is located along the respective bit line pairs in between the respective parts of said switching means of respective adjoining pairs of said memory cell array blocks. 
     
     
       11. The device of claim 10, wherein respective pairs of said pluralities of sense amplifiers, one plurality each from said two groups, are simultaneously enabled during said selecting of said word lines of said one memory cell array block in each of said first and second groups. 
     
     
       12. The device of claim 11, said column decoder means comprising two column decoders, one for each said group, each said column decoder being connected to the bit line pairs of a respective one of the memory cell array blocks. 
     
     
       13. The device of claim 11, wherein said switching control circuit includes a selection circuit to alternately operate a respective part of said switching means in said two groups.