Auxiliary decoder for semiconductor memory device

Abstract

A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a line decoder, said line decoder comprising a plurality of MOS first transistors having sources connected to a ground line, drains connected to a first node, and gates receiving respective address signals; an MOS second transistor having a source coupled to said first node, a drain coupled to a power source terminal, and a gate receiving a precharge signal; a plurality of MOS third transistors having drains connected to said first node and gates receiving a separation signal; a plurality of MOS fourth transistors, in a number equal to the number of said third transistors, having gates connected to sources of corresponding ones of said third transistors, drains receiving corresponding word line drive signals, and sources connected through corresponding fusible links to corresponding word lines; and   an auxiliary line decoder comprising a plurality of MOS fifth transistors having sources connected to said ground line and drains connected through corresponding fusible links to a second node, said fifth transistors being provided in pairs of which the two transistors of each pair receive respective inverted and uninverted address signals; an MOS sixth transistor having a source connected to said second node, a drain connected to said power source terminal and a gate receiving said precharge signal; a plurality of MOS seventh transistors having drains connected to said second node and gates receiving said separation signal; a plurality of MOS eighth transistors, in a number equal to the number of said seventh transistors, having gates connected to sources of corresponding ones of said seventh transistors, drains receiving corresponding word line drive signals, and sources connected through corresponding fusible links to corresponding auxiliary word lines.