Method and apparatus for verifying the design of digital electronic components

Abstract

A method for verifying the design of a digital electronic component in which the component is replaced by a simulation unit connected to the intended host system. The simulation unit has a memory for holding responses to stimuli from the host system. If the required response is not in the memory, it is calculated and placed in the memory, and the operation of the host system is then re-started from the beginning. In this way, the required set of responses is built up incrementally in the memory until, eventually, the operation of the host system can run to completion.

What is claimed is: 
     
       1. A method for verifying the design of a digital electronic system wherein a first part of the system is physically implemented by real hardware and a second part of the system is simulated by operating a simulator for calculating simulated responses from the second part to the first part of the system, the simulator having a memory connected to it for storing response patterns, wherein the improvement comprises the steps: (a) operating the first part of the system to perform a sequence of operations in which the first part of the system produces stimuli for the second part of the system and the first part of the system is required to receive responses from the second part of the system,   (b) reading out response patterns from said memory and applying them to the first part of the system as responses to said stimuli, and   (c) when a required response pattern is not present in the memory, storing one of the calculated simulated responses in the memory as a response pattern and than restarting said sequence of operations from a predetermined starting point.   
     
     
       2. Apparatus for verifying the design of a digital electronic system comprising: (a) means for physically implementing a first part of the system, and   (b) simulation means for simulating a second part of the system by calculating responses from the second part to the first part of the system, and   (c) a memory for holding response patterns, wherein the improvement comprises:   (d) means for reading out said response patterns from the memory to provide simulated responses from the second part of the system to the first part of the system,   (e) means operable, when a required response pattern is not present in the memory, for causing the simulation means to calculate the required next response from the second part of the system, and   (f) means for storing the calculated response in the memory as a response pattern, and then restarting operation of the system from a predetermined starting point.   
     
     
       3. A method for verifying the design of a digital electronic component wherein the component is simulated by calculating simulated responses from the component, wherein the improvement comprises the steps: (a) operating a host system to perform a predetermined sequence of operations in which it produces stimulii for the component and is required to receive responses from the component,   (b) detecting stimulii from the host system and, for each detected stimulus, examining a memory to determine whether it holds a response to that stimulus,   (c) if a response to the stimulus is held in the memory, returning that response to the host system directly from the memory, and   (d) if a response to stimulus is not held in the memory, storing one of the calculated simulated responses in the memory, and then restarting the operation of the host system form a predetermined starting point.   
     
     
       4. A method according to claim 3 wherein the responses are stored in the memory sequentially, in chronological order. 
     
     
       5. Apparatus for verifying the design of a digital electronic component, comprising: (a) a host system arranged to perform a predetermined sequence of operations in which it produces stimulii for the component and is required to receive responses from the component, and   (b) simulation means for simulating said component by calculating said responses from the component wherein the improvement comprises:   (c) a memory for holding responses to said stimuli,   (d) means for detecting a stimulus from the host system and for determining whether a response to a stimulus is already held in the memory and, if so, returning that response to the host system directly from the memory,   (e) means operative in the event that a response to a stimulus is not held in the memory, for operating said simulation means to calculate the required response to the stimulus, and   (f) means for storing the calculated response in the memory and then restarting the operation of the host system from a predetermined starting point.   
     
     
       6. Apparatus according to claim 5 including a counter for addressing the memory, means for incrementing the counter each time a stimulus is detected, so that the responses are read out of the memory sequentially, and means for resetting the counter after a response is stored in the memory.