Phase-locked sampling of a periodic signal

Abstract

A method for phase-locked sampling measurement of a periodically varying quantity. The samples are designated g(I) . . . g(I-n) and may comprise one complete period or a half of one period. The method involves adapting the sampling frequency and the sample position in relation to the quantity to be measured such that phase locking is attained, and this is done by controlling the time interval between sampling. Whether the sampling frequency needs to be increased, left unchanged or be decreased, depends on a number of decisions depending on the values of samples g(I) and g(I)-g(I-n). A device for carrying out the method is also described.

We claim: 
     
       1. A method for phase-locked sampling during measurement of a periodically varying quantity u(t) with a nominal frequency f m , the sampling being intended to take place n times per period with a sampling frequency of f s  =n·f m , the last n+1 measured sampled digital values g(I), g(I-1) . . . g(I-n) being stored in a shift register, the method being characterized in that the sampling frequency f s  is varied around f s  =n·f m  so that it will be adapted to the periodicity of the quantity to be measured in such a way that phase-locked sampling is obtained, the adaptation being based on the result of a comparison of the sampled data of g(I) and g(I-n) according to the following: the sampling frequency is increased if g(I) is ≦0 and g(I)-g(I-n) is ≦0, provided that g(I) and g(I)-g(I-n) are not both =0, and   the sampling frequency is reduced if g(I) is ≧0 and g(I)-g(I-n) is ≧0, provided that g(I) and g(I)-g(I-n) are not both =0, and   the sampling frequency is retained unchanged if any one of the following conditions is met both g(I) and g(I)-g(I-n) are zero,   g(I) is positive and g(I)-g(I-n) is negative, and   g(I) is negative and g(I)-g(I-n) is positive.     
     
     
       2. A method according to claim 1, in which the difference between the value of a sample and the value of the preceding sample is determined.   the sign of the difference is determined, and   the value of the sample, which is measured n/4 samples after the sample when the sign of the difference changes from plus to minus, is identified as g(I).   
     
     
       3. A method according to claim 1, in which the value of that sample which lies n samples before the value of that sample which is identified as g(I), is identified as the value of the sample g(I-n). 
     
     
       4. A method according to claim 2, in which the value of that sample which lies n samples before the value of that sample which is identified as g(I), is identified as the value of the sample g(I-n). 
     
     
       5. A device for carrying out the method according to claim 1 for phase-locked sampling during measurement of a periodically varying quantity n(t) with a nominal frequency f m , comprises an A/D converter, a databus, a shift register having a plurality of memory addresses, an oscillator, a first and second counter, a time delay element, a first and a second OR-element, a first, a second and a third comparator and a plurality of AND-elements, the device being characterized in that sampled digital data from the A/D converter are supplied to the memory addresses of the shift register via the databus, a sampling frequency for control of the shift register is supplied to the shift register, from the first two memory addresses of the shift register sampled digital data is supplied to the first comparator, the output of which, via the time delay element, is supplied to the first counter, the output signal of the first counter is supplied to the second counter, the second counter is supplied with a signal from the oscillator, the output signal of the second counter is supplied to the A/D convertor and the shift register, digital data from the first memory of the shift register is supplied to the second comparator and to the third comparator, to said third comparator there are also supplied digital data from the last memory address of the shift register, the output signals of the second and third comparators are supplied to a first, a second, a third, a fourth, a fifth and a sixth AND-element, the output signals from the first, second and third AND-elements being supplied to the first OR-element, the output signal of which is supplied to the first counter, and the output signal from the fourth, fifth and sixth AND-elements are supplied to the second OR-element, the output signal of which is supplied to the first counter.