Clock frequency divider circuit

Abstract

A clock frequency divider circuit for producing signals of a desired frequency (of, for example, 1.024 MHz) in response selectively to input clock pulses of two or more different predetermined frequencies, wherein control pulses are produced from and in synchronism with the input clock pulses and are fed to a frequency division network including two master-slave "D" flip-flop circuits adapted to produce a first predetermined fraction of the frequency of the control pulses in response to input clock pulses of a first frequency (of, for example, 2.048 MHz conforming to CCITT Recommendation standard) or a second predetermined fraction of the frequency of the control pulses in response to input clock pulses of a second or third frequency (of, for example, 1.536 MHz or 1.544 MHz conforming to T-1 standards). Signals with a frequency corresponding to such a first or second predetermined fraction are fed to a frequency selector network in which the frequency fraction is multiplied by a first or second predetermined multiple to achieve the desired frequency.

What is claimed is: 
     
       1. A clock frequency divider circuit for producing a signal of a desired frequency in response selectively to input clock pulses of a first predetermined frequency or input clock pulses of a second predetermined frequency, comprising (1) means for receiving first and second frequency selection signals each having first and second logic states,   (2) means for receiving a synchronizing signal of a predetermined frequency larger than each of said first and second predetermined frequencies,   (3) a clock control network which is responsive to said first frequency selection signal and to said synchronizing signal and which is to be supplied selectively with input clock pulses of said first predetermined frequency or input clock pulses of said second predetermined frequency, the clock control network being operative to produce a first control signal of a frequency which is equal to the frequency of said input clock pulses except in the presence of the first frequency selection signal of the second logic state and in the concurrent presence of said synchronizing signal, or a second control signal of a predetermined logic state in the copresence of the first frequency selection signal of the second logic state and said synchronizing signal,   (4) a frequency division network which is responsive to said second frequency selection signal and selectively to said first or second control signal and which is operative to produce a first frequency-divided signal of a frequency equal to a first predetermined fraction of said first predetermined frequency in the presence of the second frequency selection signal of the first logic state, or a second frequency-divided signal of a frequency equal to a second predetermined fraction of said second predetermined frequency in the presence of the second frequency selection signal of the second logic state, and   (5) a frequency selector network responsive to said second frequency selection signal and selectively to said first or second frequency-divided signal, said frequency selector network being operative to produce output clock pulses of a frequency equal to a first predetermined multiple of the frequency of said first frequency-divided signal in the presence of the second frequency selection signal of the first logic state, or output clock pulses of a frequency equal to a second predetermined multiple ("2") of the frequency of said second frequency-divided signal in the presence of the second frequency selection signal of the second logic state.   
     
     
       2. A clock frequency divider circuit as set forth in claim 1, in which said frequency selector network is constructed so that said first predetermined multiple is given as k which is an integer smaller than an integer m representative of the reciprocal of said first predetermined fraction and said second predetermined multiple is given as (m/n)(f 1  /f 2 ) where n is an integer representative of the reciprocal of said predetermined second fraction and f 1  and f 2  are representative of said first and second predetermined frequencies, respectively. 
     
     
       3. A clock frequency divider circuit as set forth in claim 1 or 2, in which said first control signal has first and second logic states and in which said frequency division network comprises first and second flip-flop circuits and a logic circuit intervening between the first and second flip-flop circuits, each of the first and second flip-flop circuits being responsive selectively to the first or second control signal from said clock control network and comprising a master flip-flop operative to have data latched therein in the presence of the first control signal of the first logic state or in the presence of said second control signal, and a slave flip-flop which is responsive to the data in the master flip-flop in the presence of the first control signal of the second logic state and which is to be isolated from the master flip-flop in the presence of the first control signal of the first logic state or in the presence of said second control signal, said logic circuit being operative to transfer data from the slave flip-flop of said first flip-flop circuit to the master flip-flop of said second flip-flop circuit and from the slave flip-flop of said second flip-flop circuit to the master flip-flop of said first flip-flop circuit. 
     
     
       4. A clock frequency divider circuit as set forth in claim 3, in which the master flip-flop of each of said first and second flip-flop circuits has an input terminal and an inverted output terminal and the slave flip-flop of each of said first and second flip-flop circuits has a non-inverted output terminal, the input terminal of the master flip-flop of the first flip-flop circuit being directly connected to the non-inverted output terminal of the second flip-flop circuit, the input terminal of the master flip-flop of the second flip-flop circuit being connected to the non-inverted output terminal of the first flip-flop circuit through said logic circuit. 
     
     
       5. A clock frequency divider circuit as set forth in claim 4, in which said logic circuit is operative to produce a signal of a first logic state in the presence of signals each of a first state at the non-inverted output terminals of said first and second flip-flop circuits and to produce a signal of a second logic state in the presence of a signals each of a second state at the non-inverted output terminal of at least one of said first and second flip-flop circuits.