Guard system for inverter apparatus

Abstract

An inverter using gate turn-off thyristors (GTOs) is controlled by means of pulse width modulation (PWM) to control the speed of an induction motor. If the current flowing through the induction motor becomes an overcurrent which can still be cut off by the GTOs, a gate off signal is supplied to respective GTOs to interrupt the overcurrent. If any one of arms respectively corresponding to phases is short-circuited, a gate on signal is supplied to all GTOs to distribute the short circuit current among the arms, and the main circuit is interrupted by a high-speed breaker. At this time, a simultaneous gate on signal is given priority. If the simultaneous gate on signal is present, a simultaneous gate off signal is disabled. Owing to this configuration, destruction of the GTOs due to consecutive guard operation can be prevented.

We claim: 
     
       1. A guard system for an inverter comprising: an inverter for converting DC power to AC power to be supplied to a load, said inverter comprising semiconductor switching devices;   first guard means for simultaneously cutting off said switching devices;   second guard means for simultaneously turning on said switching devices; and   means for preventing the operation of said first guard means during the operation of said second guard means.   
     
     
       2. A guard system for an inverter according to claim 1, wherein said first guard means responds to a predetermined value of a current flowing through said load. 
     
     
       3. A guard system for an inverter according to claim 2, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       4. A guard system for an inverter according to claim 2, wherein said second guard means responds to operation of means detecting a short circuit of an arm caused by simultaneous conduction of two sets of switching devices connected in series in said inverter. 
     
     
       5. A guard system for an inverter according to claim 4, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       6. A guard system for an inverter according to claim 4, wherein said arm short circuit detecting means responds to a drop in voltage across said two switching devices connected in series. 
     
     
       7. A guard system for an inverter according to claim 6, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       8. A guard system for an inverter-according to claim 1, wherein said first guard means responds to a current flowing through said load which exceeds a first predetermined value and does not exceed a second predetermined value in magnitude. 
     
     
       9. A guard system for an inverter according to claim 8, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       10. A guard system for an inverter according to claim 1, wherein said first guard means responds to a current flowing through said load which exceeds a first predetermined value and does not exceed a second predetermined value, and wherein said first predetermined value is a maximum value under normal conditions and said second predetermined value is a current value which can be interrupted by said switching devices. 
     
     
       11. A guard system for an inverter according to claim 10, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       12. A guard system for an inverter according to claim 1, wherein said second guard means responds to operation of means detecting a short circuit of an arm caused by simultaneous conduction of two sets of switching devices connected in series in said inverter. 
     
     
       13. A guard system for an inverter according to claim 12, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       14. A guard system for an inverter according to claim 12, wherein said arm short circuit detecting means responds to a drop in voltage across said two switching devices connected in series. 
     
     
       15. A guard system for an inverter according to claim 14, wherein said semiconductor swiching devices comprise gate turn-off thyristors. 
     
     
       16. A guard system for an inverter according to claim 1, wherein said semiconductor switching devices comprise gate turn-off thyristors. 
     
     
       17. A guard system for an inverter according to claim 1, wherein said preventing means comprises two NAND gates connected in series as a first stage and a second stage in an ON-OFF signal transmission path and wherein the NAND gate of the first stage is supplied with a simultaneous gate off signal and the NAND gate of the second stage is supplied with a simultaneous gate on signal. 
     
     
       18. A guard system for an inverter comprising: a three-phase inverter supplied with DC power from an aerial conductor through a switch and a high-speed breaker, said three-phase inverter including six GTOs connected as three series connected pairs, each pair comprising an arm of a three phase bridge configuration;   a three-phase induction motor supplied with power by said three-phase inverter, said induction motor being connected to center taps of said three series connected pairs of said GTOs;   an electric car driven by said induction motor;   pulse width modulator means;   gate drive circuits for turning on and turning off said GTOs on the basis of an ON-OFF signal sent out from said modulator means;   first guard means for simultaneously turning off said GTOs, in response to a current of said induction motor larger than the maximum current at normal conditions and not larger than the interruptible current of the GTOs;   second guard means for simultaneously turning on all of said GTOs, in response to simultaneous conduction of one series connected pair of said GTOs; and   means for preventing the operation of said first guard means, in response to the operation of said second guard means.