Formation of self-aligned stacked CMOS structures by lift-off

Abstract

A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off. The gate aligned recess is then filled with a dopant masking material by deposition and etching, which dopant masking material thereafter defines during implant or diffusion an upper field effect transistor channel region self-aligned with the common gate electrode. The characteristics of the upper field effect transistor can be improved by applying laser recrystallization techniques.

We claim: 
     
       1. A process for fabricating in an active region of a substrate an aligned, three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode, comprising the steps of: forming in the active region of a semiconductor substrate over a first channel defined between first source/drain regions a relatively thick lift-off material layer coextensive with an underlining gate electrode layer, together forming sidewalls at the channel ends;   forming a first dielectrical layer, over the integrated circuit structure, characterized by the presence of an accentuated etchability of the first dielectric layer in the regions covering the sidewalls of the lift-off material layer;   selectively etching first dielectric layer material covering the sidewalls of the lift-off material layer to expose the lift-off material;   selectively removing the lift-off material and first dielectric formed thereover to form a recess in correspondence with the gate electrode layer;   forming a conformal layer of a semiconductor material over the structure to retain a recess in correspondence with the gate electrode layer;   forming a region of dopant masking material in the recess in correspondence with the gate electrode layer; and   doping the semiconductor material in the presence of the region of dopant masking material to form in the semiconductor material layer a second channel under the dopant masking region and second source/drain regions outside the dopant masking region.   
     
     
       2. The process recited in claim 1, wherein the first dielectric layer formed over the integrated circuit structure is silicon dioxide with stressed sidewall regions. 
     
     
       3. The process recited in claim 2, wherein the first dielectric layer is materially thicker than the gate electrode layer. 
     
     
       4. The process recited in claim 3, wherein the relatively thick lift-off material layer is materially thicker than the conformal layer of semiconductor material. 
     
     
       5. The process recited in claim 4, wherein a gate dielectric layer is formed over the gate electrode before the step of forming a conformal layer of semiconductor material. 
     
     
       6. The process recited in claim 2, wherein the lift-off material layer is composed of silicon nitride and the gate electrode layer is composed of a polysilicon. 
     
     
       7. The process recited in claim 6, wherein the selective etch of the first dielectric layer material covering the sidewalls utilizes an isotropic etch highly preferential to stressed silicon dioxide over unstressed silicon dioxide. 
     
     
       8. The process recited in claim 6, wherein the conformal layer of semiconductor material is composed of undoped or lightly doped polysilicon. 
     
     
       9. The process recited in claim 8, including after the step forming a conformal layer of a semiconductor material the step of recrystallizing the conformal layer of the semiconductor material layer. 
     
     
       10. The process recited in claim 8, wherein the step of forming a region of dopant masking material in correspondence with the gate electrode layer is comprised of forming a planarizing oxide layer and etching the layer to the plane of the polysilicon. 
     
     
       11. The process recited in claim 8, wherein the conformal layer of semiconductor material is selectively patterned and interconnected by metallization following the doping step. 
     
     
       12. A process for fabricating in an active region of a substrate an aligned, three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode, comprising the steps of: forming over an active region in the semiconductor substrate a gate dielectric layer covered in succession by a gate electrode layer and a relatively thick lift-off material layer;   forming a photoresist masking layer corresponding to the pattern of the gate electrode;   etching the lift-off material layer and the gate electrode layer in the presence of the masking layer to pattern the layers and expose sidewalls thereof;   doping the substrate active region in the presence of the masking provided by the patterned layers to form self-aligned first source/drain regions;   forming an oxide layer, over the integrated circuit structure, characterized by the presence of an accentuated etchability of stressed oxide covering the sidewalls of the lift-off material layer;   selectively etching the stressed oxide covering the sidewalls of the lift-off material to expose the lift-off material;   selectively removing the lift-off material and oxide formed thereover to form a recess in correspondence with the gate electrode layer;   forming a gate oxide layer over the gate electrode;   forming a conformal polysilicon layer over the structure;   forming a region of dopant masking material in the recess in correspondence with the gate electrode layer; and   doping the conformal polysilicon layer in the presence of the region of dopant masking material to form in the polysilicon layer a channel under the dope masking region and second source/drain regions outside of the dopant mask.   
     
     
       13. The process recited in claim 12, wherein the oxide layer is materially thicker than the gate electrode layer. 
     
     
       14. The process recited in claim 13, wherein the relatively thick lift-off material layer is materially thicker than the conformal polysilicon layer. 
     
     
       15. The process recited in claim 14, wherein the lift-off material layer is composed of silicon nitride and the gate electrode layer is composed of polysilicon. 
     
     
       16. The process recited in claim 15, wherein the selective etch of the oxide layer covering the sidewalls utilizes an isotropic etch highly preferential to stressed over unstressed oxide. 
     
     
       17. The process recited in claim 16, wherein the step of forming a region of dopant masking material in correspondence with the gate electrode is comprised of forming a planarizing oxide layer and etching the layer to the plane of the polysilicon layer. 
     
     
       18. The process recited in claim 14, including after the step of forming a conformal layer of polysilicon the step of recrystallizing the polysilicon layer.