Multi-function bus

Abstract

This disclosure depicts a multi-function bus for use with a central processor system, user devices having user interfaces and a host switching interface unit. The multi-function bus has a first pre-determined number of transmit and receive lines connecting the central processing system, the user interfaces and the host interfacing unit. A second pre-determined number of channels on each of the transmit and receive lines is provided for on the multi-function bus. A multi-function bus includes the transfer of information to and from the host switching system both in a serial mode and in a parallel mode on the multi-function bus.

What is claimed is: 
     
       1. A multi-function bus for use with a central processor system, user devices having user interfaces and a host switching interface unit, said multi-function bus comprising: a first pre-determined number of transmit and receive lines connecting a central processing system, the user interfaces and the host switching interface unit;   a second pre-determined number of channels on each of said transmit and receive lines, said channels grouped on said multi-function bus in a frame, each frame having a predetermined number of bits and each bit having a predetermined bit period, each of such channels having end bits and appearing serially within said frame, said frame also including a frame synchronization bit;   means for transferring information to and from said host switching interface in a serial mode on said multi-function bus; and   means for transferring information between said central processding system and said user interfaces in a a parallel mode on said multi-function bus;   said multi-function bus operated in a serial mode, and in a parallel mode, by said first and second means for transferring information by utilizing one-half of each bit period for serially transmission and the other one-half bit period for parallel transmission.