Process for fabricating a self-aligned bipolar transistor

Abstract

Using a single mask pattern on a semiconductor substrate, a doped base contact region adjacent to the surface of the substrate, a buried insulating region below the base contact region, and an insulating layer on the base contact region, and optionally, a metal or metal silicide base-electrode-taking-out layer on the base contact region, are formed, respectively. Doped emitter and intrinsic base regions are formed below the mask pattern. A collector region is defined by the base contact region and the buried insulating layer to be inside thereof, i.e., below the mask pattern. Thus, a bipolar transistor is formed in a size that is essentially necessary, thereby reducing the collector-base capacitance, the base resistance, and the size of the device.

We claim: 
     
       1. A process for fabricating a bipolar transistor, comprising the steps of: preparing a semiconductor substrate;   defining a first doped region of a first conductivity type adjacent to the surface of the semiconductor substrate;   forming a mask layer on the first doped region, the mask layer having a pattern corresponding to that of an active area of the transistor to be formed;   locally implanting ions into the first doped region, using the mask layer as a mask, to form a buried insulating layer;   locally introducing dopants in the first doped region at the surface of the substrate and above the buried insulating layer, using the mask layer as a mask, to form a base contact region of a second conductivity type opposite to the first conductivity type;   forming an intrinsic base region of the second conductivity type in the first doped region adjacent to the base contact region;   forming an emitter region of the first conductivity type in the intrinsic base region and adjacent to the surface of the substrate; and   using the first doped region of the first conductivity type below the intrinsic base region as a collector.   
     
     
       2. A process according to claim 1, wherein the step of forming the buried insulating region is prior to the step of forming the base contact region. 
     
     
       3. A process according to claim 1, wherein the step of forming the base contact region is prior to the step of forming the buried insulating layer. 
     
     
       4. A process according to claim 1, wherein the step of forming the intrinsic base region is prior to the step of forming the emitter region. 
     
     
       5. A process according to claim 1, wherein the step of forming the emitter region is prior to the step of forming the intrinsic base region. 
     
     
       6. A process according to claim 1, further comprising the step of locally forming a second insulating layer above the base contact region. 
     
     
       7. A process according to claim 6, wherein the second insulating layer is formed by locally insulating the surface of the base contact region, using said mask layer as a mask. 
     
     
       8. A process according to claim 7, further comprising the step of opening a window in the second insulating layer to expose the surface of the base contact region in the window, followed by forming a base electrode in contact with the base contact layer through the window. 
     
     
       9. A process according to claim 6, further comprising the step of locally forming a metal or metal silicide layer on the base contact layer before the step of forming the second insulating layer. 
     
     
       10. A process according to claim 9, wherein the metal or metal silicide layer is formed by local deposition of a metal or metal silicide, onto the base contact region or by local deposition of a metal on the base contact region followed by silicidation of the deposited metal. 
     
     
       11. A process according to claim 9, wherein the second insulating layer is formed by making the surface of the metal or metal silicide layer insulating. 
     
     
       12. A process according to claim 11, wherein the second insulating layer is formed by anodizing the surface of the metal or metal silicide layer. 
     
     
       13. A process according to claim 9, wherein at least a part of the second insulating layer is formed by depositing an insulating material above the metal or metal silicide layer. 
     
     
       14. A process according to claim 13, wherein after depositing the insulating material above the metal or metal silicide layer and above the first doped region where at least a part of the mask layer is removed, anisotropic etching is conducted to remove the insulating material except the side wall portion of the metal or metal silicide layer, whereby an insulating wall having a desired lateral thickness of the insulating wall is formed at the side wall portion of the metal or metal silicide layer. 
     
     
       15. A process according to claim 1, wherein the semiconductor substrate is of silicon. 
     
     
       16. A process according to claim 1, wherein the buried insulating region is formed by implanting oxygen or nitrogen ions there. 
     
     
       17. A process according to claim 10, wherein the locally deposited metal or metal silicide is a refractory metal or a silicide thereof.