Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor

Abstract

A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-shaped and dielectrically isolated region of silicon material resulting from the formation of an isolation trench in the silicon. The trench is filled with a plastic material, such as polyimide. The capacitor is formed by the isolated region of silicon material which functions as the first capacitor plate, a doped polysilicon layer provided on the vertical walls of the mesa serving as the second capacitor plate and a thin dielectric layer interposed between the two plates serving as the capacitor's dielectric. Since the polysilicon is wrapped around the periphery of the mesa as a coating on the vertical sidewalls thereof, it gives rise to a large storage capacitance without an increase in the cell size.

What is claimed: 
     
       1. A method of forming a high capacitance and low leakage mesa-shaped capacitor structure in a semiconductor structure comprising the steps of: (a) providing a semiconductor structure comprised of a substrate of a first type of conductivity having an epitaxial layer of an opposite conductivity type formed thereon, said layer having a heavily doped buried region of said opposite type of conductivity, said buried region serving as an electrode plate of the capacitor structure, said buried region being provided with a reach-through region in correspondence with the locations where a capacitor is to be formed;   (b) forming a pattern of substantially vertical isolation trenches extending from one surface of said structure into said substrate through said epitaxial layer, thereby delineating a plurality of mesa shaped isolated regions of semiconductor material;   (c) thermally oxidizing the sidewalls of said trenches to provide silicon dioxide layer serving as the dielectric for said capacitor structure;   (d) forming a thin layer of doped polysilicon on the resulting structure;   (e) forming a dual passivating layer of silicon dioxide and silicon nitride, in order, on the resulting structure;   (f) removing by using a photolithographic process the nitride-oxide-polysilicon composite layer from everywhere except the trench sidewalls and the horizontal top surface of the mesa to define the other electrode plate of the capacitor structure and a polysilicon tab of the said other electrode, said tab to be subsequently used as the contact area of said other electrode plate;   (g) subjecting the resulting semiconductor structure to an oxidizing ambient to oxidize the exposed edge portions of the polysilicon layer;   (h) removing the nitride-oxide dual layer at the location of said contact area to expose said polysilicon tab;   (i) exposing a surface portion of said reachthrough region; and   (j) making ohmic contacts with both said polysilicon tab and the reach-through region.   
     
     
       2. The method of claim 1 further including the step of filling said trenches for device isolation purposes with a material selected from a group consisting of polyimide, polysilicon and silicon dioxide. 
     
     
       3. The method of claim 2 wherein said substrate is of the P- type of conductivity. 
     
     
       4. The method of claim 3 wherein said epitaxial layer is P-type. 
     
     
       5. The method of claim 3 wherein said buried region is an N+ blanket layer formed at the lower portion of said epitaxial layer by heavily doping. 
     
     
       6. The method of claim 3 further comprising merging said buried region and said reach-through region into a single N+ region abutting the sidewalls of the trenches. 
     
     
       7. The method of claim 1 wherein the step (d) further comprises the steps of: depositing a layer of intrinsic polysilicon by low pressure chemical vapor deposition to a thickness of about 200 nm; and   doping the polysilicon layer with phosphorous dopant to reach a sheet resistivity of about 50-100 ohms/square.   
     
     
       8. The method as in claim 7 wherein the concentration of phosphorous is at least 5×10 19  atoms/cc. 
     
     
       9. The method as in claim 8 wherein the thickness of said capacitor dielectric is in the range of about 30-100 nm.