Semiconductor memory device

Abstract

There is disclosed an NPN transistor comprising collector region of N conductivity type, base region of P conductivity type formed in the collector region, and emitter region of N conductivity type formed in the collector region. The collector and emitter regions define therebetween a planar PN junction. The NPN transistor further comprises a field plate electrode layer, when the transistor is viewed from above, extending from the periphery of the base region to the collector region. The field plate electrode layer comprises P conductivity semiconductor portion and N conductivity semiconductor portion. The P conductivity semiconductor portion is on the side of the base region. The N conductivity semiconductor portion is on the side of the collector region.

What is claimed is: 
     
       1. A semiconductor device comprising: a first semiconductor layer of a first conductivity type:   a semiconductor region of a second conductivity type formed in said first semiconductor layer, said first semiconductor layer and said semiconductor region defining therebetween a planar junction;   an insulation layer of a predetermined pattern formed on said first semiconductor layer and said semiconductor region; and   a second semiconductor layer formed on said insulation layer, constituting a field plate electrode layer, said second semiconductor layer, when viewed through said insulation layer, extending outwardly from the periphery of said semiconductor region to overlay a portion of said first semiconductor layer, said second semiconductor layer including a first semiconductor portion of said second conductivity type and a second semiconductor portion of said first conductivity type, said first semiconductor portion being disposed adjacent to said semiconductor region, when viewed through said insulation layer, said second semiconductor protion being disposed adjacent to said first semiconductor layer, when viewed through said insulation layer, said first and second semiconductor portions defining therebetween a junction extending through the entire thickness of said second semiconductor layer, and said junction defined between said first and second semiconductor portions, when viewed through said insulation layer, overlaying said first semiconductor layer outside said semiconductor region.   
     
     
       2. A semiconductor device according to claim 1, further comprising a second semiconductor region of said first conductivity type formed in said first recited semiconductor region, said second semiconductor region and said first semiconductor region defining therebetween a junction. 
     
     
       3. A semiconductor device according to claim 2, in which said first semiconductor layer constitutes the collector region of a bipolar transistor, said first semiconductor region constitutes the base region of said bipolar transistor, and said second semiconductor region constitutes the emitter region of said bipolar transistor. 
     
     
       4. A semiconductor device according to claim 1, further comprising: a first electrode for connecting said semiconductor region and said first semiconductor portion and a second electrode for connecting said first semiconductor layer and said second semiconductor portion; and   in which said planar junction defined between said first semiconductor layer and said semiconductor region is reverse biased through said first and second electrodes, and said junction defined between said first semiconductor portion and said second semiconductor portion is reverse biased through said first and second electrodes.   
     
     
       5. A semiconductor device according to claim 2, further comprising: a first electrode for connecting said second semiconductor region and said first semiconductor portion, a second electrode for connecting said first semiconductor layer and said second semiconductor portion, and a third electrode contacting said first recited semiconductor region; and   in which said planar junction defined between said first semiconductor layer and said first recited semiconductor region is reverse biased through said first and second electrodes, said junction defined between said first semiconductor portion and said second semiconductor portion is reverse biased through said first and second electrodes, and said junction defined between said first recited semiconductor region and said second semiconductor region is forward biased through said first and third electrodes.   
     
     
       6. A semiconductor device according to claim 1, in which said second semiconductor layer is made of polysilicon. 
     
     
       7. A semiconductor device according to claim 2, in which said first semiconductor layer constitutes the drain region of a MOS transistor, said first recited semi-conductor region constitutes the back-gate region of said MOS transistor, and said second semiconductor region constitutes the source region of said MOS transistor. 
     
     
       8. A semiconductor device according to claim 7, further comprising a gate electrode formed on said insulation layer and above that portion of said back-gate region which is between said first semiconductor layer and said second semiconductor region, said gate electrode being provided at a same step for forming said second semiconductor layer by patterning a same semiconductor layer. 
     
     
       9. A semiconductor device comprising: a first semiconductor layer of a first conductivity type;   a semiconductor region of a second conductivity type formed in said first semiconductor layer, said first semiconductor layer and said semiconductor region defining therebetween a planar junction;   
     
     
       an insulation layer of a predetermined pattern formed on said first semiconductor lyer and said semiconductor region; and a second semiconducctor layer formed on said insulation layer, constituting a field plate electrode layer, said second semiconductor layer, when viewed through said insulation layer, extending outwardly from the periphery of said semiconductor region to overlay a portion of said first semiconductor layer, said second semiconductor layer comprising a plurality of first semiconductor portions of said second conductivity type and a plurality of second semiconductor portions of said first conductivity type, said first semiconductor portions and second semiconductor portions, when viewed through said insulation layer, being alternately disposed from the periphery of said semiconductor region outwardly toward said first semiconductor layer for providing a plurality of junctions therebetween, each of said plural junctions being defined between adjacent first and second semiconductor portions each said first semiconductor portion being disposed toward said semiconductor region, when viewed through said insulation layer, each said second semiconductor portion being disposed toward said first semiconductor layer, when viewed through said insulation layer, said plural junctions extending over the entire thickness of said second semiconductor layer, and said plural junctions defined between said first and second semiconductor portions being, when viewed through said insulation layer, above said first semiconductor layer and outside said semiconductor region.   
     
     
       10. A semiconductor device according to claim 9, further comprising a second semiconductor region of said first conductivity type formed in said first recited semiconductor region, said second semiconductor region and said first semiconductor region defining there-between a junction. 
     
     
       11. a semiconductor device according to claim 10, in which said first semiconductor layer constitutes the collector region of a bipolar transistor, said first semiconductor region constitutes the base region of said bipolar transistor, and said second semiconductor region constitutes the emitter region of said bipolar transistor. 
     
     
       12. A semiconductor device according to claim 9, further comprising: a first electrode for connecting said semiconductor region and one of said first semiconductor portions, said a second electrode for connecting said first semiconductor layer and one of said plural second semiconductor portions, which, when viewed through said insulation layer, is situated further from said semiconductor region than is said one of the first semiconductor portions; and   in which said planar junction defined between said first semiconductor layer and said semiconductor region is reverse biased through said first and second electrodes, and said plural junctions defined between said first semiconductor portions and said second semiconductor portions are reverse biased through said first and second electrodes.   
     
     
       13. A semiconductor device according to claim 10, further comprising: a first electrode for connecting said semiconductor regions and one of said first semiconductor portions and a second electrode for connecting said first semiconductor layer and one of said second semiconductor portions, which, when viewed through said insulation layer, is situated further from said semiconductor regions than is said one of the first semiconductor portions;   and in which said planar junction defined between said first semiconductor layer and said first recited semiconductor region is reverse biased through said first and second electrodes, and said plural junctions defined between said first semiconductor portions and said second semiconductor portions are reverse biased through said first and second electrodes, and said junction defined between said first recited semiconductor region and said second semiconductor region is forward biased through said first and second electrodes.   
     
     
       14. A semiconductor device according to claim 9, in which said second semiconductor layer is made of polysilicon. 
     
     
       15. A semiconductor device according to claim 10, in which said first semiconductor layer constitutes the drain region of a MOS transistor, said first recited semiconductor region constitutes the back-gate region of said MOS transistor, and said second semiconductor region consitutes the source region of said MOS transistor. 
     
     
       16. A semiconductor device according to claim 15, further comprising a gate electrode formed on said insulation layer and above that portion of said back-gate region which is between said first semiconductor layer and said second semiconductor region, said gate electrode being provided at a same step for forming said second semiconductor layer by patterning a same semi-conductor layer.