Semiconductor memory device in form of shift register with two-phase clock signal supply

Abstract

A semiconductor memory device in the form of a shift register is supplied with two-phase clock signals. One of the two-phase clock signal lines is connected to even order shift register elements of the shift register, and the other of the two-phase clock signal lines is connected to odd order shift register elements of the shift register. Each of the shift register elements includes an output node, a gate connected between the output node and a clock signal supplying node, a charge-up circuit responsive to the output signal of the preceding shift register element for preliminarily charging a control node of the gate, and a discharge circuit responsive to the output of the succeeding shift register element for releasing the charge of the control node of the gate.

I claim: 
     
       1. A semiconductor memory device in the form of a shift register with two clock signal lines comprising: a sequence of shift register elements; and   first and second clock signal lines for supplying said shift register elements with first and second clock signals of first and second phases respectively, said first and second clock signals having waveforms which do not overlap each other;   said first clock signal line being connected to even order shift register elements of said shift register, said second clock signal line being connected to odd order shift register elements of said shift register;   each of said shift register elements comprising:   an output node for producing an output signal;   a clock signal supplying node for receiving one of said first and second clock signals;   a gate connected between said output node and said clock signal supplying node and having a control gate;   a charge-up circuit responsive to the output signal of the preceding shift register element for preliminary charging said control node of said gate; and   a discharge circuit responsive to the output of the succeeding shift register element for releasing the charge of said control node of said gate.   
     
     
       2. A device according to claim 1, wherein each of said shift register elements further comprises a latch circuit having a potential maintenance function connected to said output node of each of said shift register elements. 
     
     
       3. A device according to claim 1, wherein each of said shift register elements further comprises a latch circuit having a potential maintenance function connected to the input side of each of said shift register elements. 
     
     
       4. A device according to claim 2, wherein each of said shift register elements further comprises a latch circuit having a potential maintenance function connected to the input side of each of said shift register elements.