Randomized motor drive

Abstract

The circuit provides damping for digitally controlled devices where the provision of power pulses in response to sensing a given device parameter may result in a regularity of pulses that causes a resonant condition with a frequency that interferes with other device functions or induces error conditions. The circuit shown randomizes to a motor by random gating of a sequence of commands retained in a shift register. Random gating from the shift register positions occurs through the use of a counter driven by an oscillator, independent of other device functions and clocking circuits, in conjunction with an enabling circuit from a random digitized data source that enables or disables counter advance by the oscillator. In the disk drive environment shown, randomizing has no significant effect on the closely regulated speed since the corrective commands occur during each sector of revolution or about thirty-six hundred times per second and motor rotational inertia precludes any meaningful change during a sector rotation.

I claim: 
     
       1. In a device for digitally controlling the supply of power to a powered unit where the requirement for a power pulse is regularly ascertained during recurring times and a pulse is supplied in response to the indicated power requirement, randomizing means comprising means for recording one of the requirement for power and the lack of a need for a power pulse during a current time period and a predetermined plurality of successive, immediately preceding previous periods;   means for randomly selecting one of said periods; and   gating means for transmitting a power pulse to said unit connected to the output of said one of said periods with said gate being enabled if said one of said periods records a requirement for power.   
     
     
       2. The device of claim 1 wherein said means for recording is a shift register having a number of positions equal to the sum of the current period and the predetermined plurality of successive, immediately preceding previous periods in which a first logic level is entered when power is required and a second logic level is entered when power is not required. 
     
     
       3. A motor speed regulation system for a motor wherein each revolution is divided into a plurality of sectors comprising means for determining the speed during a sector of rotation and generating a first signal value if the determined speed is below a threshold value and generating a second signal value if the determined speed is not below said threshold value;   storage means for retaining a predetermined number of the most recent first and second signal values;   gate means for supplying a pulse to said motor for a predetermined period; and   randomizing means for randomly enabling one of said predetermined number of most recent signal values to be communicated to said gate means, said gate means being enabled when said signal has said first value and not being enabled when said signal has said second value.   
     
     
       4. The motor speed regulation system of claim 3 wherein said storage means comprises a shift register having a number of positions equal to said predetermined number of most recent signal values and said randomizing means connects one of said shift register positions to said gate means. 
     
     
       5. The motor speed regulation system of claim 4 wherein said randomizing means includes oscillator means which is not synchronized with the other elements of the motor speed regulation system and cooperating circuit means for interconnecting said gate means and one of said shift register positions in an unpredictable sequence. 
     
     
       6. A motor speed regulation system for a motor driving a data storage disk media wherein each revolution is divided into a plurality of sectors comprising means for sensing the velocity during a sector of rotation and generating a first binary value if the determined speed is below a threshold value and generating a second binary value if the speed is not below said threshold value;   shift register storage means having a predetermined number of storage positions for retaining said binary values;   loading means for loading the indicated one of said binary values into said shift register during each sector of motor travel;   gate means for supplying a power pulse to said motor; and   randomizing means for randomly connecting one of said shift register positions to said gate means, whereby said gate means may be enabled when said shift register position contains said first value and may not be enabled when said one shift register position contains said second value.   
     
     
       7. The motor speed regulation system of claim 6 wherein said randomizing means includes oscillator means, not synchronized with remainder of said motor speed regulation system, in cooperation with a digitized signal sequence to randomly select said shift register positions for connection to said gate means in an unpredictable sequence. 
     
     
       8. The motor speed regulation system of claim 7 wherein both the elapsed times between successive sectors and between randomizing oscillator means pulses is less than 1 millisecond.