Two-stage digital logic circuits including an input switching stage and an output driving stage incorporating gallium arsenide FET devices

Abstract

Digital logic driving stage circuitry is provided connected between ground and a single voltage with an enhancement mode type field effect transistor and a depletion mode type field effect transistor connected source to drain in series between the single voltage and ground. The gate of the enhancement mode type field effect transistor is the input of the logic signal and the gate of the depletion mode type field effect transistor is connected to ground, with the output at the connection between the transistors. A family of digital logic circuits is provided with circuit units made up of an enhancement mode logic input, depletion mode load circuitry stage and an enhancement mode input grounded source follower load driving stage.

Having thus described my invention, what I claim as new and desire to secure by Letters Patent is: 
     
       1. A logic circuit unit comprising in combination a logic input switching stage having an output terminal and at least one input terminal,   a logic output driving stage having an input and an output terminal,   said logic input switching stage having said output terminal thereof directly connected to said input terminal of said logic output driving stage, and said directly connected logic input switching stage and logic output driving stage being connected between voltage and ground,   said logic input switching stage comprising at least one enhancement mode FET formed in gallium arsenide semiconductor material with said at least one input terminal thereof connected to the gate electrode of said at least one enhancement mode gallium arsenide FET,   said logic output driving stage comprising an enhancement mode FET formed in gallium arsenide semiconductor material with said input terminal thereof connected to the gate terminal of said enhancement mode gallium arsenide FET,   each said stage having a depletion mode FET formed in gallium arsenide semiconductor material having the source and gate thereof connected together serving as a load on each said enhancement mode gallium arsenide FET,   said at least one input terminal connected to said gate electrode of said at least one enhancement mode FET in said logic input switching stage being responsive to a logic variable signal for producing an output signal on said output terminal of said logic output driving stage, said output terminal being connected at the point between said enhancement mode FET and said depletion mode FET load element in said logic output driving stage.   
     
     
       2. A logic circuit unit comprising in combination a logic stage connected between ground and a voltage comprising   an enhancement mode logic switching input stage with an output node and including three enhancement mode field effect transistors connected source to drain in parallel between ground and said output node, and having a separate logic signal variable at each gate thereof and operable to change the voltage at said output node to the proximity of the ground voltage level in the presence of at least one logic input signal,   said output node connected to the source electrode of a depletion mode field effect transistor and to the gate electrode of said depletion mode field effect transistor, the drain electrode of said depletion mode transistor being connected to said voltage,   a driving stage connected between said voltage and ground including   a depletion mode field effect transistor element having the source electrode and the gate electrode thereof connected to said ground,   an enhancement mode field effect transistor element having one ohmic electrode thereof connected to said voltage, having the gate thereof connected to said output node of said logic stage and having the logic circuit unit output connected to the source electrode of said enhancement mode field effect transistor and to the drain electrode of said depletion mode field effect transistor.   
     
     
       3. The circuit unit of claim 2 wherein said enhancement mode transistor threshold voltage is +0.05 volts, said depletion mode transistor threshold voltage is -0.65 volts and said voltage is +1.5 volts. 
     
     
       4. The logic circuit unit of claim 2 wherein each said depletion mode type and said enhancement mode type field effect transistor is formed in gallium arsenide semiconductor material. 
     
     
       5. The logic circuit unit of claim 4 wherein said enhancement mode trnasistor threshold voltage is +0.05 volts, said depletion mode transistor threshold voltage is -0.65 volts and said voltage is +1.5 volts.