US4732871AExpiredUtility

Process for producing undercut dummy gate mask profiles for MESFETs

79
Assignee: IBMPriority: Jul 11, 1986Filed: Mar 30, 1987Granted: Mar 22, 1988
Est. expiryJul 11, 2006(expired)· nominal 20-yr term from priority
Inventors:Peter BuchmannVolker GrafPeter D. HohTheodor O. MohrPeter Vettiger
H10P 76/4085H10P 50/283H10P 14/69433H10P 14/6927H10P 14/6682H10P 14/68H10D 64/0125H10P 14/6336H10D 64/017H10D 30/0614
79
PatentIndex Score
59
Cited by
18
References
28
Claims

Abstract

Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G). Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.

Claims

exact text as granted — not AI-modified
Having thus described our invention, what we claim as new, and desire to secure by Letters Patent is: 
     
       1. A process for fabricating undercut mask profiles for use in semiconductor device manufacturing comprising the steps of: depositing a first layer of dielectric material on the surface of a substrate in a plasma enhanced chemical vapor deposition reactor at a first plasma excitation frequency to impart a given etch rate to said first layer,   depositing a second layer of dielectric material on said first layer at a second plasma excitation frequency to impart an etch rate lower than said given etch rate to said second layer,   patterning said first and second layers such that at least one vertical edge of each of said layers is exposed, and   etching said first and second layers at said at least one vertical edge to remove portions of said first layer at a rate higher than the rate at which portions of said second layer are removed.   
     
     
       2. A process according to claim 1 wherein said first and second layers of dielectric material are nitrides. 
     
     
       3. A process according to claim 1 wherein said substrate is made of a semiconductor material. 
     
     
       4. A process according to claim 1 wherein said first and second layers of dielectric material are made of silicon nitride. 
     
     
       5. A process according to claim 1 wherein said first and second layers of dielectric material are made of boron nitride. 
     
     
       6. A process according to claim 1 wherein said first and second layers of dielectric material are made of nitrides selected from the group consisting of silicon and boron nitride. 
     
     
       7. A process according to claim 1 wherein said first plasma excitation frequency is in a range of 1 to 50 MHz and said second excitation frequency is below 100 kHz. 
     
     
       8. A process according to claim 1 wherein said substrate is made of silicon. 
     
     
       9. A process according to claim 1 wherein said substrate is made of gallium-arsenide. 
     
     
       10. A process according to claim 1 wherein the step of depositing a first layer of dielectric material includes the steps of: introducing into said reactor a gas comprising NH 3  :N 2  :SiH 4  in the proportions 18:3:55, respectively, at a pressure of about 0.1 Pa,   heating said substrate to a temperature of 300° C., and   exciting said gas at a frequency of 13 MHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said substrate.   
     
     
       11. A process according to claim 1 wherein the step of depositing a second layer of dielectric material includes the steps of: introducing into said reactor a gas comprising N 2  :SiH 4  in the proportions 4:50, respectively, at a pressure of about 0.1 Pa,   heating said substrate to a temperature of 300° C., and   exciting said gas at a frequency of 50 kHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said first layer.   
     
     
       12. A process according to claim 1 wherein the step of patterning said first and second layers includes the steps of: forming a photoresist mask on the surface of said second layer, and   etching said first and second layers to remove portions of said layers not covered by said mask.   
     
     
       13. A process according to claim 1 wherein the step of etching said first and second layers includes the step of exposing said at least one vertical edge of said first and second layers to a wet chemical etch so that portions of said first layer are removed at a higher rate than portions of said second layer. 
     
     
       14. A process according to claim 1 wherein the step of etching said first and second layers includes the steps of exposing said at least one vertical edge of said first and second layers to a dry plasma etch so that portions of said first layer are removed at a higher rate than portions of said second layer. 
     
     
       15. A process for fabricating undercut mask profiles for use in the fabricating of a fully self-aligned field effect transistor which includes a gate and source and drain elements formed in a semiconductor substrate having a current channel disposed therebetween comprising the steps of: depositing a first layer of nitride on the surface of said substrate in a plasma enhanced chemical vapor deposition reactor at a first plasma excitation frequency to impart a given etch rate to said first layer,   depositing a second layer of nitride on said first layer at a second plasma excitation frequency to impart an etch rate lower than said given etch rate to said second layer,   patterning said first and second layers such that at least one vertical edge of each of said layers is exposed, and   etching said first and second layers at said at least one vertical edge to remove portions of said first layer at a rate higher than the rate at which portions of said second layer are removed and provide an undercut mask structure having a T-shaped cross section.   
     
     
       16. A process according to claim 15 further including the steps of: ion implanting to form source and drain regions within said semiconductor substrate at both ends of said current channel using said T-shaped structure as a mask,   depositing ohmic contact metallization onto said source and drain regions,   applying and planarizing a reflowable dielectric to embed said T-shaped structure,   removing the portion of said dielectric that covers the top of said T-shaped structure,   removing said T-shaped structure to expose the surface region over said current channel where said gate electrode is to be formed,   depositing a gate metallization, and   removing the remaining portion of said dielectric together with those sections of said gate metallization deposited on top of it.   
     
     
       17. A process according to claim 15 wherein said first and second layers of nitride are made of silicon nitride. 
     
     
       18. A process according to claim 15 wherein said first and second layers of nitride are made of boron nitride. 
     
     
       19. A process according to claim 15 wherein said first and second layers of nitrides are nitrides selected from the group consisting of silicon and boron nitride. 
     
     
       20. A process according to claim 15 wherein said first plasma excitation frequency is in a range of 1 to 50 MHz and said second excitation frequency is below 100 kHz. 
     
     
       21. A process according to claim 15 wherein said semiconductor is silicon. 
     
     
       22. A process according to claim 15 wherein said semiconductor is galliumarsenide. 
     
     
       23. A process according to claim 15 wherein the step of depositing a first layer of nitride includes the steps of: introducing into said reactor a gas comprising NH 3  :N 2  :SiH 4  in the proportions 18:3:55, respectively, at a pressure of about 0.1 Pa,   heating said substrate to a temperature of 300° C., and   exciting said gas at a frequency of 13 MHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said substrate.   
     
     
       24. A process according to claim 15 wherein the step of depositing a second layer of nitride includes the steps of: introducing into said reactor a gas comprising N 2  :SiH 4  in the proportions 4:50, respectively, at a pressure of about 0.1 Pa,   heating said substrate to a temperature of 300° C., and   exciting said gas at a frequency of 50 kHz and a power of 75 watts to deposit a layer of silicon nitride at a rate of 20-30 nm/min. on said first layer.   
     
     
       25. A process according to claim 15 wherein the step of patterning said first and second layers includes the steps of: forming a photoresist mask on the surface of said second layer, and   etching said first and second layers to remove portions of said layers not covered by said mask.   
     
     
       26. A process according to claim 15 wherein the step of etching said first and second layers includes the step of exposing said at least one vertical edge of said first and second layers to a wet chemical etch so that portions of said first layer are removed at a higher rate than portions of said second layer. 
     
     
       27. A process according to claim 15 wherein the step of etching said first and second layers includes the steps of exposing said at least one vertical edge of said first and second layers to a dry plasma etch so that portions of said first layer are removed at a higher rate than portions of said second layer. 
     
     
       28. A process according to claim 16 whrein said gate forms a Schottky barrier at an interface with said current channel.

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