Data processing apparatus for controlling reading out of operands from two buffer storages

Abstract

The data processing apparatus has first and second storages each independently accessible. An instruction unit applies a fetch request on a one-operand instruction to the first storage, and a fetch request on a two-operand instruction to the first and second storages. In case of a fetch request on a two-operand instruction, a storage control unit instructs the instruction unit to produce again a fetch request if one of the first and second storages is busy, and execute reading the operands in the order of decoding of instructions.

What is claimed is: 
     
       1. A data processing apparatus for fetching an operand indicated by an instruction from a storage which includes a main storage and a buffer store which stores a copy of frequently used instructions and data stored in the main storage, comprising: (a) first and second buffer storages in said buffer store and each being independently accessible;   (b) instruction means for decoding instructions received in sequence and for outputting for each instruction a fetch request and at least one operand address according to whether said instruction is a one-operand instruction or a two-operand instruction, including means responsive to a one-operand instruction for providing said operand address to said first buffer storage and responsive to a two-operand instruction for providing one operand address to said first buffer storage and another operand address to said second buffer storage; and   (c) storage control means for controlling the sequence of operation of said instruction means, including means connected to said buffer store for supervising the busy/free status of each of said first and second buffer storages, means for transferring a re-request signal to said instruction means upon a condition that said first buffer storage is busy when the fetch request calls for a one-operand instruction or a condition that at least one of said buffer storages is busy when said fetch request calls for a two-operand instruction, and means for indicating a busy state of said buffer store during a predetermined cycle when said re-request signal is transferred to said instruction means;   wherein said instruction means further includes means responsive to said re-request signal for outputting said fetch request and said operand address once again to said storage control means and said buffer store in the sequence of receipt of instructions for decoding by said instruction means.   
     
     
       2. A data processing apparatus according to claim 1, wherein said instruction means includes: first hold means for holding said fetch request and said operand address for said first buffer storage in the order of decoding of instructions; second hold means for holding said fetch request and said operand address for said second buffer storage in the order of decoding of instructions; and third hold means for indicating whether said fetch request is for both storages or not; and means for outputting the contents of said first, second and third hold means in the order of decoding of instructions.   
     
     
       3. A data processing apparatus according to claim 2, wherein said storage control means further includes means responsive to the output from said third hold means for identifying whether said fetch request calls for a one-operand instruction or a two-operand instruction.