Multifunction bus to user device interface circuit

Abstract

A multifunction bus to user device interface circuit interfaces a user device having an adjunct processing unit and transmit and receive lines with a multi-function bus having predetermined channels and control time slots. The interface circuit has an internal processor for controlling data flow and is connected to the adjunct processing unit through an internal interface means for communicating control, address and data signals. A serial connection memory for channel selection is operatively connected to the internal processor as well as a parallel connection memory for channel selection. An I/O port interfaces the control time slots on the multi-function bus and is operatively connected to the internal processor. The multi-function bus interface means provides for communicating with the channel of the multi-function bus.

What is claimed is: 
     
       1. A interface circuit for use in interfacing a user interface device having an adjunct processing unit and transmit and receive lines with a multi-function bus having predetermined channels and control time slots, said interface circuit comprising: internal processor means for controlling data flow and operatively connected to said adjunct processing unit through an internal interface means for communicating control, address and data signals;   serial connection memory means for channel selection operatively connected to said internal processor means;   I/O port means for interfacing the control time slots on the multi-function bus and operatively connected to said internal processor means;   multi-function bus interface means for communicating with the channels on the multi-function bus;   serial multiplexer means for allowing read and write access to said serial connection memory means operatively connected to said serial connection memory means, to the user interface device trasnmit and receive lines, and to said multi-function bus interface;   parallel multiplexer means for allowing read and write access to a parallel connection memory means and is operatively connected to said parallel connection memory means, to user interface device transmit and receive lines, and to said multi-function bus interface means; and   clock means for receiving a predetermined external clock signal and a reset signal for synchronization operatively connected to said internal processor for receiving predetermined clock frequencies and outputting internal clock signals and strobe signals, to said serial connection memory means, said parallel connection memory means, said serial multiplexer means, said parallel multiplexer means and said multi-function bus interface means.   
     
     
       2. The device described in claim 1 wherein said multi-function bus also has extended transmit and receive lines ad wherein said network interface LSI further comprises: packet connection memory means for time slot selection on the multi-function bus operatively connected to said internal processor;   packet multiplexer means for allowing read and write access to said packet connection memory means operatively connected to said packet memory means;   packet extended interface means for communicating with said extended transmit and receive lines on the multi-function bus operatively connected to said packet multiplexer means.   
     
     
       3. The device described in claim 2 wherein said packet connection memory means, said packet multiplexer means and said packet extended interface means are operatively connected to said clock means. 
     
     
       4. The device described in claim 2 wherein said packet extended interface means comprises: an interface port for transferring addresses, control and data signals with the adjunct processing unit in the user interface device;   a dual port memory for linking the address, control and data signals from the interface port operatively connected to said internal processor;   an address identification circuit operatively connected to said dual port memory and to said internal processor and presenting enable signals to said serial connection memory means, said parallel connection memory means, said packet connection memory means, said I/O port means and said clock means.   
     
     
       5. The device described in claim 1 wherein said serial connection memory means comprises: a memory having five areas for selecting, respectively, two serial transmit lines and three serial receive lines of the user interface device, said memory further having a predetermined number of address locations corresponding to the predetermined number of channels in the multi-function bus, said memory operatively connected to said serial multiplexer means;   an address multiplexer operatively connected to said memory to allow for read and write access to said memory areas;   an address counter operatively connected to said address multiplexer and to said internal processor for sequentially addressing and reading said memory;   an address latch operatively connected to said memory and to said internal processor for randomly writing to a selected address in said memory;   an input data latch operatively connected to said internal processor and to an input data multiplexer, said input data multiplexer operatively connected to said memory.   
     
     
       6. The device described in claim 1 wherein said parallel connection memory means comprises: a memory having six areas for selecting, respectively, two transmit time slots and four receive time slots, said memory further having a predetermined number of address locations, said memory operatively connected to said parallel multiplexer;   an address multiplexer operatively connected to said memory to allow for read and write access to said memory areas;   an address counter operatively connected to said address multiplexer and to said internal processor for sequentially addressing and reading said memory; and   an address latch operatively connected to said memory and to said internal processor for randomly writing to a selected address in said memory.