Screening of gate oxides on semiconductors

Abstract

Testing of the gate oxides of all the transistors of a single die in a silicon wafer to be diced into a plurality of dice in a single operation is effected at an intermediate stage of the fabrication process by providing a metal layer contacting selectively each of the gate electrodes of a die at an intermediate stage of the processing and providing between the layer and the wafer a voltage of amplitude insufficient to cause significant tunneling current through good gate oxides but sufficient to cause significant tunneling current through defective gate oxides.

What is claimed: 
     
       1. In the manufacture of integrated circuits which involves forming from a silicon wafer a plurality of individual dice each of which includes an integrated circuit comprising a plurality of MOS transistors each of which has a polycrystalline silicon gate electrode overlying a gate oxide layer, the process of testing simultaneously the gate oxides of a group of transistors in a single die area comprising the steps of preparing the silicon wafer to include polycrystalline gate electrodes over gate oxide regions to be tested,   depositing an insulating layer over the wafer and patterning this layer to expose selectively portions of the gate electrodes of the group of transistors to be tested simultaneously,   depositing a metal layer to form electrical connections to the gate electrodes where exposed, patterning the metal layer so that each discrete portion of the metal layer covers portions only of the gate electrodes of the group of transistors whose gate oxide regions are to be tested in parallel together, then applying a voltage between said metal layer an the silicon wafer for passing current simultaneously through the gate oxide regions, and measuring the current to detect abnormally large currents in any gate oxide of the chosen transistors in the die area.   
     
     
       2. The process of claim 1 in which the voltage applied has a value which results in insignificant current flow through a defect-free gate oxide but significant current flow through a defective gate oxide. 
     
     
       3. The process of claim 2 in which the group of transistors to be tested simultaneously are all the transistors in a single die area. 
     
     
       4. The process of claim 1 which includes the further steps of removing the patterned metal layer after the measuring step, forming additional openings in the insulating layer to expose active regions of the silicon wafer where connections to a first level metal are desired, and depositing the first level metal to form connections to both the polycrystalline gate electrodes and exposed active regions of the silicon wafer. 
     
     
       5. A method for testing gate members during the manufacture of semiconductor devices which comprises: (a) providing a semiconductor wafer substrate having source, drain and gate members thereon;   (b) providing an insulating layer on said substrate, source, drain and gate members;   (c) coating said insulating layer with a photoresist layer and imagewise exposing said photoresist layer through an exposure mask which corresponds to said gate members, and developing said photoresist layer to remove at least a portion of the photoresist only at the insulating layer locations on the gate member locations;   (d) removing at least a part of the insulating layer portions which lie on the gate members and leaving the insulating layer portions which do not lie on said gate members;   (e) depositing an electrically conductive metal layer on said insulating layer so as to form an electrical connection between said metal layer and each gate member but no direct electrical connection between said metal layer and said substrate;   (f) dividing said metal layer into a plurality of sections corresponding to a plurality of semiconductor dice; and providing a voltage potential between the individual metal layer sections and said substrate and measuring any current flow therebetween;   (g) removing said metal section from said substrate; and   (h) removing the insulating layer from the regions where metal contact to active or other regions is desired.