RF transistor package with capacitor

Abstract

A semiconductor device comprising a conductive layer; an insulting layer mounted on the conductive layer and having an opening; terminals deposited on the insulating layer; an active semiconductor element mounted on the conductive layer or the insulating layer, and; a capacitor mounted on the conductive layer. In this device, a path between the semiconductor element and the capacitor is very short and the conductive layer serves as a heat sink.

We claim: 
     
       1. A high frequency semiconductor amplifier requiring a bypass capacitance for high frequency currents and a heat sink for high power operation, comprising: a first, heat sink conductive layer having a main surface and having an electrical ground connection;   an insulating layer of a first predetermined thickness formed on the main surface of the heat sink conductive layer and having a generally, centrally located opening therein exposing therethrough a corresponding portion of the main surface of the heat sink conductive layer;   a second conductive layer formed on the exposed portion of the main surface of the first, heat sink conductive layer and of a second predetermined thickness;   an active semiconductor element, comprising a field effect transistor having source, gate and drain regions and corresponding connection points, mounted on and bonded to the second conductive layer and of a third predetermined thickness;   a bypass capacitor having top and bottom electrodes and of a fourth predetermined thickness, mounuted on and bonded to the second conductive layer in closely spaced relationship to the semiconductor element and defining a first alignment direction relatively to the semiconductor element and the opening in the insulting layer, the bottom electrode of the bypass capacitor being electrically connected to the second conductive layer, the first heat sink conductive layer and the electrical ground connection;   each of the third and fourth predetermined thickness of the active semiconductor element and the bypass capacitor, respectively, being substantially less than either of the first and second predetermined thickness of the first, heat sink conductive layer and the insulating layer, respectively;   a first metallized layer formed on the insulating layer and aligned in the first alignment direction, with the bypass capacitor positioned between the first metallized layer and the semiconductor element;   means for providing a series electrical connection of the source connection point of the semiconductor element, the top electrode of the bypass capacitor, and the first metallized layer;   second and third metallized layers formed on the insulating layer in a second alignment direction, transverse to the first alignment direction, and aligned with and spaced apart from the semiconductor element by at least the opening in the insulating layer;   means for providing an electrical connection between the drain connection point of the semiconductor element and the second metallized layer;   means for providing an electrical connection between the gate connection point of the semiconductor element and the third metallized layer; and   a source terminal plate oriented in the first alignment direction and bonded to the first metallized layer, and drain and gate terminal plates oriented in the second alignment direction and respectively bonded to the second and third metallized layers, the source, drain and gate terminal plates extending laterally from the first heat sink conductive layer and the insulating layer to provide external electrical connections to the amplifier.   
     
     
       2. A high frequency semiconductor amplifier as recited in claim 1, wherein: the gate terminal plate comprises an input terminal for receiving high frequency input signals and the drain terminal plate comprises an output terminal for the amplified, high frequency output signals of the amplifier; and   said means for connecting the source connection point and the top electrode of the bypass capacitor, and for connecting the top electrode of the bypass capacitor and the first metallized layer comprise respective, first and second wires, the first wire and the bypass capacitor providing a low impedance path to the electrical ground connection for high frequency currents from the source region of the active semiconductor element and thereby stabilizing the amplification of the amplifier with respect to the received high frequency input signals and the amplified, high frequency output signals.   
     
     
       3. A high frequency semiconductor amplifier as recited in claim 1, wherein: the first and second predermined thickness of the insulating layer and the second conductive layer are substantially the same, and the second and third predetermined thickness of the active semiconductor element and the bypass capacitor, respectively, are substantially the same and substantially less than either of the first and second predetermined thicknesses, such that the respective upper surfaces of the active semiconductor element, the bypass capacitor, and the insulating layer are substantially in a common plane.   
     
     
       4. The device of claim 2, wherein the parasitic inductance for propagation of said high frequency current between the source and said top electrode of the capacitor is effecitvely limited by the length of the first connecting wire in comparison to the length and respective parasitic inductance of said second wire. 
     
     
       5. The device of cliam 2, wherein the parasitic inductance for propagation of said high frequency current between the source and said top electrode of the capacitor is effectively limited by the length of the first connecting wire in comparison to the length and respective parasitic inductance of said second wire. 
     
     
       6. The device of claim 2, wherein the parasitic inductance for propagation of said high frequency current between the source and said top electrode of the capacitor is effectively limited by the length of the first connecting wire in comparison to the length and respective parasitic inductance of said second wire. 
     
     
       7. The device of claim 6, said first and second conducting layers serving as a heat sink for the active semiconductor element.