Digital pipelined heterodyne circuit

Abstract

A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.

I claim: 
     
       1. A digital heterodyne circuit comprising: (a) a data input line for receiving a sequence of digitized data signals;   (b) digital sine and co-sine function generator means, each having m outputs for generating m-bit digital coefficients, one bit on each output, a predetermined time intervals as a function of time corresponding to sine ωt and co-sine ωt, respectively, where ω is a predetermined frequency;   (c) m-stage arithmetic means for multiplying said data signals by said digital coefficients; and   (d) delay means connecting said output of said function generator means for a corresponding stage of said arithmetic means for providing each respective bit of a digital coefficient to each such corresponding stage of said arithmetic means simultaneously with the arrival at each such corresponding stage of a predetermined one of said data signals.   
     
     
       2. The digital heterodyne circuit of claim 1 wherein said delay means comprises a plurality of shift registers, one for each said output of said function generator means, each of said shift registers having a respective different number of sequential stages, the number of sequential stages in each of said shift registers corresponding to the rank in significance of each output of each function generator means to which each said shift register is connected. 
     
     
       3. The digital heterodyne circuit of claim 2 wherein a first stage of said arithmetic means comprises means for converting input data signals to their two's complements, and for multiplying each of said two's complements by the most significant bit of said sine and cosine coefficients to form a first arithmetic stage product. 
     
     
       4. The digital heterodyne circuit of claim 1 wherein an m-bit digital coefficient is generated by said sine and cosine function generator means as each digitized data signal is received on said data input line. 
     
     
       5. A digital heterodyne circuit comprising: (a) a data input line for providing a digitized data input signal;   (b) digital sine and cosine function generator means for generating m-bit digital coefficients at a predetermined frequency;   (c) first arithmetic stage means for digitally multiplying the most significant bit of each m-bit coefficient, from said function generator means by a first data input signal, thereby producing a first product output;   (d) second arithmetic stage means for digitally multiplying the next most significant bit of said m-bit coefficients from said function generator means by said first output product, thereby producing a second output product;   (e) m th  arithmetic stage means for multiplying the least significant bit of said m-bit coefficients from said function generator means by the (m-l)th output product, thereby producing a heterodyned data signal; and   (f) triangular shift register means for providing each bit of said m-bit coefficients to each of said arithmetic stage means in timed relation such that said data input signal is processed sequentially by each of said arithmetic stage means simultaneously with the sequential processing of other data input signals.   
     
     
       6. The digital heterodyne circuit of claim 5 wherein said digital sine and cosine function generator means comprise separate sine and cosine function generators for producing separate sets of m-bit digital coefficients. 
     
     
       7. The digital heterodyne circuit of claim 6 wherein said triangular shift register means comprises a plurality of shift registers, one for each bit of said digital sine and co-sine coefficients, wherein each shift register includes a number of stages corresponding to the ranking in significance of each bit of said coefficients.