Semiconductor memory device formed of a SOI-type transistor and a capacitor

Abstract

A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET and a capacitor. The FET has an SOI structure. The capacitor is composed of a dielectric layer as an insulating layer for the SOI structure, an upper capacitor electrode as a semiconductor layer for the SOI structure, and a lower capacitor electrode as a semiconductor substrate. The substrate is biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.

I claim: 
     
       1. A semiconductor memory device comprising: a transistor formed in a semiconductor layer which is formed on an insulating layer, said insulating layer being formed on a well region formed in a semiconductor substrate, said semiconductor substrate being a first conductivity type, said well region being a second conductivity type opposite to said first conductitivy type, said transistor having a silicon on insulator structure where said silicon corresponds to said semiconductor layer and said insulator corresponds to said insulating layer; and   a capacitor composed of a dielectric layer formed from said insulating layer, an upper capacitor electrode formed from said semiconductor layer, and a lower capacitor electrode formed from said well region wherein said dielectric layer is sandwiched between said upper and lower capacitor electrodes; the well region having a reverse bias to that of said substrate and being biased with a voltage at an intermediate level between a first storage voltage and a second storage voltage.   
     
     
       2. A semiconductor memory device according to claim 1, wherein said transistor is field effect transistor comprising a source region and a drain region formed in said semiconductor layer and a gate electrode formed on a gate insulating layer on said semiconductor layer. 
     
     
       3. A semiconductor memory device according to claim 1, wherein the dielectric layer of said capacitor is a thin portion of said insulating layer which is thinner than a remaining portion of said insulating layer. 
     
     
       4. A semiconductor memory device according to claim 3, wherein said capacitor is a trench type. 
     
     
       5. A semiconductor memory device according to claim 4, wherein said thin portion of said insulating layer is formed on a groove surface of said trench, and said semiconductor layer is composed of a polycrystalline silicon portion formed on said insulating layer. 
     
     
       6. A semiconductor memory device according to claim 2, wherein said semiconductor layer is a polycrystalline silicon layer. 
     
     
       7. A semiconductor memory device according to claim 2, wherein said semiconductor layer is a single crystalline silicon layer. 
     
     
       8. A semiconductor memory device according to claim 1, wherein said second storage voltage is a supply voltage and said first storage voltage is a ground voltage. 
     
     
       9. A semiconductor memory device according to claim 8, wherein said intermediate level voltage is a half of the supply voltage. 
     
     
       10. A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type;   a well region of a second conductivity type, opposite said first conductivity type, disposed in a surface portion of said semiconductor substrate;   an insulating layer composed of a first portion and a second portion and formed on said semiconductor substrate, said first portion being thinner than said second portion;   a semiconductor layer formed on said insulating layer;   a transistor formed in said semiconductor layer, said transistor having a silicon on insulator structure, where said silicon corresponds to said semiconductor layer and said insulator corresponds to said second portion of said insulating layer;   a capacitor composed of a dielectric layer of said first portion of said insulating layer, an upper capacitor electrode formed from said semiconductor layer, and a lower capacitor electrode formed from said well portion wherein said dielectric layer is sandwiched between said upper capacitor electrode and said lower capacitor electrode; said well region having a reverse bias to that of said substrate, said well region being biased with an intermediate voltage between a first storage voltage and a second storage voltage.   
     
     
       11. A semiconductor memory device according to claim 10, wherein said transistor is a field effect transistor comprising a source region and a drain region formed in said semiconductor layer and a gate electrode formed on a gate insulating layer on said semiconductor layer. 
     
     
       12. A semiconductor memory device according to claim 10, wherein said capacitor is a trench type. 
     
     
       13. A semiconductor memory device according to claim 11, wherein said semiconductor layer is a polycrystalline silicon layer. 
     
     
       14. A semiconductor memory device according to claim 11, wherein said semiconductor layer is a single crystalline silicon layer. 
     
     
       15. A semiconductor memory device according to claim 10, wherein said second storage voltage is a supply voltage and said first storage voltage is a ground voltage. 
     
     
       16. A semiconductor memory device according to claim 15, wherein said intermediate voltage is a half of the supply voltage.