Direct voltage multiplier capable of being integrated into a semiconducting structure

Abstract

A direct voltage multiplier which can be integrated into a semiconducting structure. The multiplier comprises a capacitor which is charged and discharged at the pace of a clock signal, with a depletion-mode MOS transistor mounted as a resistor and enabling the capacitor to be discharged. The invention makes it possible to integrate the multiplier into a semiconducting substrate and can be used, in particular, to control a VD MOS.

What is claimed is: 
     
       1. Multiplier of a direct voltage with a predetermined value in relation to a reference point, comprising at least one cell of the voltage doubler type, operating by the charging and discharging of a capacitor and controlled by a clock signal, the multiplier being designed to give a control signal to a device that has an input capacity of a predetermined value, multiplier comprising: electronic means by which a first electrode of the capacitor can be set at the potential of the reference point according to the clock signal,   a diode linked to a second electrode of the capacitor, the diode providing for the passage of charging current under the effect of the direct voltage of predetermined value, this charge taking place when the first electrode of the capacitor is set at the potential of the reference point,   a resistor linking the common point between the diode and the capacitor to the device to be controlled, the resistor having a resistance and the clock signal having a pulse ratio such that the charging time of the capacitor is smaller than its discharging time, said capacitor charging to said predetermined value of said direct voltage only after application of plural clock pulses of said clock signal.   
     
     
       2. Multiplier according to the claim 1, wherein the resistance of the said resistor is about 10 times greater than the output resistance of the said electronic means, the pulse ratio of the clock signal being such that the charging time of the capacitor is 4 to 9 times smaller than its discharging time. 
     
     
       3. Multiplier according to the claim 1, wherein the resistor linked to the device to be controlled is made by means of a depletion-mode MOS transistor having its gate linked to one of its two other electrodes. 
     
     
       4. Multiplier according to the claim 3, wherein the device to be controlled is a VD MOS made from an N type substrate, the substrate also comprising a first P type well by which the said depletion-mode transistor can be made and a second P type well by which the said capacitor can be made. 
     
     
       5. Multiplier according to the claim 4, wherein the first well is taken to the potential of the said direct voltage with a determined value, the said diode being then formed by the junction that exists between the P type region of the first well and the N type region of the depletion-mode MOS transistor which is linked to the capacitor. 
     
     
       6. Multiplier according to the claim 1, wherein the said electronic means comprise an inverter.