Interleaved memory addressing system and method using a parity signal

Abstract

A high performance interleaved memory addressing system and method. A plurality of banks of random access memory devices are provided. The appropriate bank for a given memory address is selected based upon the parity among a preselected set of address bits including the least significant bit. A parity signal for selection of a memory bank is produced by a parity signal generation circuit, preferably a logic circuit. Typically, more than two memory banks would be employed, utilizing at least two parity signal generation circuits, each corresponding to respective least significant bits of the memory address. The output signals from the parity circuits are combined in a decoder to select the memory bank.

What is claimed is: 
     
       1. A system for addressing a plurality of banks of random-access memory devices, comprising: (a) means for providing a memory address having a predetermined number of address bits, greater than one;   (b) means, responsive to a predetermined set of said address bits including the least significant bit, for producing a parity signal representative of the parity among said set of address bits; and   (c) means, responsive to said parity signal, for selecting one of said banks of memory devices based upon said parity signal.   
     
     
       2. The system of claim 1 wherein said means for producing a parity signal comprises a parity generator having, as one input, said least significant address bit and, as another input, a predetermined selection of more significant address bits. 
     
     
       3. The system of claim 2 wherein said parity generator comprises a parity signal generation logic circuit. 
     
     
       4. The system of claim 3 wherein said means for selecting one of said banks of memory devices comprises decoder means for converting a binary digital signal to one of a plurality of signals corresponding respectively to said banks of memory devices. 
     
     
       5. A method for addressing a plurality of banks of random-access memory devices, comprising: (a) providing a memory address having a predetermined number of address bits, greater than one;   (b) producing a parity signal representative of the parity among a predetermined set of said address bits including the least significant address bit; and   (c) selecting one of said banks of memory devices based upon said parity signal.