Programmable logic array having an on/off sense function

Abstract

A programmable logic array includes a plurality of semiconductor memory elements, such as FAMOSs, arranged in the form of an array and a sense circuit for receiving data out from the memory elements during read out mode. The present programmable logic array is so structured that the sense circuit is rendered operative for a predetermined time period every time when an input signal to the array changes its state thereby allowing to minimize the power consumption.

What is claimed is: 
     
       1. A programmable logic array comprising: a storing means for storing a program having a desired logic function, said storing means including a plurality of reprogrammable, non-volatile semiconductor memory elements arranged in the form of a matrix defined by input lines and product term lines;   an input circuit connected to said storing means for supplying a selection signal to said input lines in response to an input signal supplied thereto;   edge sensing means connected to receive an output from said input circuit for detecting a timing of change of state of said input signal;   sensing means connecting to receive an output from said storing means; and   sense timing generating means connected between said edge sensing means and said sensing means for generating and supplying a sense activation signal to said sensing means to enable said sensing means for a predetermined time period upon detection of a timing of change of state of said input signal by said edge sensing means.   
     
     
       2. The programmable logic array of claim 1 wherein said plurality of memory elements are arranged in the form of NAND gates. 
     
     
       3. The programmable logic array of claim 1 further comprising product term line selecting means for selecting one of said product term lines in response to a control signal. 
     
     
       4. The programmable logic array of claim 3 further comprising a write circuit connected to said sensing means and said product term line selecting means, said write circuit causing said sensing means to be inhibited and said product term line selecting means to be operative when said array is in a programming mode; whereas, said write circuit causes said sensing means to be non-inhibited and said product term line selecting means to be inoperative when said array is in a read mode.