Multi-task execution control system

Abstract

In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.

What is claimed is: 
     
       1. A multi-task execution control system for a microcomputer having only a single central processor unit comprising: memory means for storing a plurality of independently programmed tasks, said plurality of independently programmed tasks including a plurality of task control commands;   said single central processor unit (CPU) executing said plurality of tasks; and   multi-task support processor means, external from and operatively connected to said central processor means and responsive to said task control commands, for controlling the switching and communication of said plurality of tasks for execution by said central processing unit;   said central processor unit, upon execution of an activation task control command included in an independently programmed task, sending said activation task control command to said multi-task support processor means;   said multi-task support processor means controlling the switching of and the communication between said plurality of tasks under the direction of said activation task control command independently of the architecture of said central processor unit.   
     
     
       2. A system, as recited in claim 1, wherein said multi-task support processor means includes, first memory means for storing control programs for controlling the switching and communication between said plurality of tasks,   interface-means, operatively connected to said central processor unit for sending data to and receiving data from said central processor means,   second memory means, connected to said interface means for storing system configuration data received from said central processing unit, and   control means, responsive to said control programs and said task control command received from said central processor unit, for controlling the switching and communication between said plurality of tasks.   
     
     
       3. A system, as recited in claim 2, wherein said second memory means stores priority data corresponding to said plurality of tasks, and said control means controls the switching between said plurality of tasks in accordance with said priority data.   
     
     
       4. A system, as recited in claim 2, further comprising, input/output means, external from and operatively connected to said central processor means, for inputting data to said central processor unit from an external device and outputting data from said central processor means to said external device. 
     
     
       5. A system, as recited in claim 2, wherein said control means initiates switching between said plurality of tasks by causing said interface means to receive or transmit said plurality of tasks to said central processor unit.