Circuit for testing the bus structure of a printed wiring card

Abstract

This circuit provides for testing the bus structure (address and data buses) of a printed wiring card. This circuit provides an inexpensive means for off line detection of low impedance paths between leads of bus oriented printed wiring cards. This circuit is particularly useful for testing high lead density printed wiring cards, such as, microprocessor or memory related printed wiring cards. This circuit automatically tests all possible combinations of bus leads for a shorted fault condition. This circuit operates without the application of any power to the printed wiring card to be tested. For the detection of any shorted fault leads, the identity of the shorted leads is displayed visually. In addition, for a shorted fault lead, a determination is made as to whether the shorted leads are address bus leads or data bus leads. A visual display indicates whether the particular printed wiring card has successfully passed all the tests

What is claimed is: 
     
       1. A circuit for testing the bus structure of a printed wiring card, said circuit comprising: pattern generation means being cyclically operated to produce pluralities of logic values corresponding to each lead of an address bus and a data bus;   memory means connected to said pattern generation means via said address and data bus, said memory means being operated to store at least two copies of said pluralities of logic values at a location corresponding to each of said pluralities logic values of said address bus;   means for connecting said bus structure of said printed wiring card to said address bus and to said data bus, said means for connection being operated to affect one copy of the logic values of said address bus corresponding to any shorted leads of said bus structure of said printed wiring card; and   detection means connected to said pattern generation means and to said memory means, said detection means being operated to compare said two stored copies of said logic values and to indicate the identity of a plurality of shorted leads of said bus structure of said printed wiring card.   
     
     
       2. A circuit for testing the bus structure of a printed wiring card as claimed in claim 1, said pattern generation means including: clock means for producing a signal of a predetermined frequency; and   counter means connected to said clock means and being cyclically operated to produce a first plurality of signals which indicate the address of the memory location to be written and being further operated to produce a second plurality of signals which indicate the identity of each particular lead of said address bus and said data bus.   
     
     
       3. A circuit for testing the bus structure of a printed wiring card as claimed in claim 2, said pattern generation means further including pattern production means connected to said counter means via a first plurality of leads and a second plurality of leads, and said pattern production means connected to said memory means via data leads, said pattern production means being operated to cyclically produce predetermined data patterns corresponding to each address input via said first plurality of leads and to transmit said data patterns to said memory means for storage via said data leads. 
     
     
       4. A circuit for testing the bus structure of a printed wiring card as claimed in claim 3, said pattern generation means further including: driver means connected to said second plurality of leads and being operated to retransmit said second plurality of signals; and   switching means connected to said first plurality of leads and to said data leads, said switching means being operated to transmit said first plurality of signals and said data signals to said memory means.   
     
     
       5. A circuit for testing the bus structure of a printed wiring card as claimed in claim 4, wherein there is further included buffering means connected to said counter means, to said memory means, to said switching means and to said detection means, said buffering means being operated to retransmit said first plurality of signals to said memory means and to said switching means. 
     
     
       6. A circuit for testing the bus structure of a printed wiring card as claimed in claim 5, said memory means including memory control means connected to said counting means via said first and second plurality of leads, to said buffering means, said memory control means being operated to produce a plurality of memory control signals including a memory read/write signal. 
     
     
       7. A circuit for testing the bus structure of a printed wiring card as claimed in claim 6, said memory means further including first memory device means connected to said pattern production means, to said memory control means and to said buffering means, said first memory device means being operated in response to said memory read/write signal of said memory control means to store said data patterns of said pattern production means at the address of said first plurality of signals. 
     
     
       8. A circuit for testing the bus structure of a printed wiring card as claimed in claim 7, said memory means further including second memory device means connected to said memory control means, to said pattern production means and to said means for connecting, said second memory device means being operated in response to said read/write signal of said memory control means to store said data patterns at the affected address location. 
     
     
       9. A circuit for testing the bus structure of a printed wiring card as claimed in claim 8, said means for connecting including low pass filter means connected to said switching means and to said bus structure of said printed wiring card, said low pass filter means being operated to remove high frequency noise from each of the signals of said bus structure of said printed wiring card. 
     
     
       10. A circuit for testing the bus structure of a printed wiring card as claimed in claim 9, said means for connecting further including gating means connected to said switching means, to said low pass filter means, to said bus structure of said printed wiring card and to said second memory device means said gating means being operated to combine said transmitted address of said buffering means with said bus structure of said printed wiring card and to transmit said combined address to said second memory device means. 
     
     
       11. A circuit for testing the bus structure of a printed wiring card as claimed in claim 10, said gating means including AND gating means. 
     
     
       12. A circuit for testing the bus structure of a printed wiring card as claimed in claim 11, said detection means including comparison means connected to said first and second memory device means and to said memory control means, said comparison means being operated in response to said memory control means to compare the contents of corresponding locations of said first and second memory device means and to produce an error indication for a miscomparison of any locations corresponding. 
     
     
       13. A circuit for testing the bus structure of a printed wiring card as claimed in claim 12, said detection means further including first error detection means connected to said comparison means and being operated to store an indication of a first detected error indication. 
     
     
       14. A circuit for testing the bus structure of a printed wiring card as claimed in claim 13, said detection means further including second error detection means connected to said comparison means and being operated to store up to five additional detected error indications subsequent to said first detected error indication. 
     
     
       15. A circuit for testing the bus structure of a printed wiring card as claimed in claim 14, said detection means further including second gating means connected between said buffering means and said second error detection means, said second gating means being operated to combine said first plurality of address leads. 
     
     
       16. A circuit for testing the bus structure of a printed wiring card as claimed in claim 15, said second gating means including OR gating means. 
     
     
       17. A circuit for testing the bus structure of a printed wiring card as claimed in claim 16, said detection means further including monitor means connected to said counter means and to said comparison means, said monitor means being operated to produce an address fail signal, a data fail signal and an all test pass signal. 
     
     
       18. A circuit for testing the bus structure of a printed wiring card as claimed in claim 17, 1 wherein there is further included first display means connected to said first error detection means and to said counter means via said second plurality of signals, said first error detection means being operated to display the identity of a first shorted lead. 
     
     
       19. A circuit for testing the bus structure of a printed wiring card as claimed in claim 18, wherein there is further included: register means connected to said second error detection means, said register means being operated to store up to five detected error indications; and   second display means connected to said register means and being operated to display up to five said detected error indications.   
     
     
       20. A circuit for testing the bus structure of a printed wiring card as claimed in claim 19, wherein there is further included: third display means connected to said monitor means and being operated in response to said address fail signal to indicate visually the failure of an address lead of said printed wiring card;   fourth display means connected to said monitor means and being operated in response to said data fail signal to produce a visual indication of a failure of a data lead of said printed wiring card; and   fifth display means connected to said monitor means via said all tests pass signal and being operated to visually display an indication that said address and data tests have been successfully completed.   
     
     
       21. A circuit for testing the bus structure of a printed wiring card as claimed in claim 20, said means for connecting further including: attachment means being selectively connectable to components of said printed wiring card having connections to said address and to said data buses; and   cable means connected between said attachment means and said low pass filter means for transmitting each of said address and data bus signals to said low pass filter means.   
     
     
       22. A circuit for testing the bus structure of a printed wiring card as claimed in claim 21, wherein there is further included enclosure means for containing said circuit for testing the bus structure of a printed wiring card.