Programmable data security circuit for programmable logic device

Abstract

An architecture security fuse circuit is disclosed for securing the architecture of a configurable programmable logic device. The storage element of the circuit is a floating gate transistor cell. Data stored in the cell is determined by the amount of charge trapped within the oxide-isolated polysilicon floating gate region. The security fuse is initialized (erased) during device fabrication to allow access to device architectural data. Such initialization is accomplished by a technique that the device user cannot duplicate, via an extra probe pad accessible only during wafer probe. To deter the effects of floating gate charge loss which may occur during subsequent fabrication steps, the fuse circuit is adapted to provide a reduced memory cell read voltage, thus providing greater margin against thermally defeating the security fuse. A regenerative feature is provided to strengthen the erased cell during every device "clear" cycle. Once the security fuse is programmed, the data defining the device architecture may not be interrogated or altered, and the memory cell is unchanged by the regenerative feature.

What is claimed is: 
     
       1. A security circuit for preventing the erasure, programming, or interrogation of predetermined electrically erasable memory cells in an integrated circuit programmable logic device when such programmable logic device is in an edit mode wherein selected electrically erasable cells of the programmable logic can be erased, programmed, or interrogated, comprising: electrically erasable means for storing security data having first and second states;   latching means responsive to said security data for providing a latching means output having first and second states, said latching means output having the same state as said security data except during the edit mode when said latching means output is latched to the same state of said security data prior to the programmable logic device being in the edit mode;   programming means responsive to control signals and said latching means output for electrically erasing said electrically erasable means to initialize said security data to said first state and for programming said security data to said second state in a selected edit mode, said programming means being disabled from resetting said security data to said first state after said security data is programmed to said second state; and   means for disabling access to the predetermined electrically erasable memory cells in response to said second state of said latching means output when the programmable logic device is in the edit mode.   
     
     
       2. The security circuit of claim 1 wherein said electrically erasable means comprises a floating gate transistor. 
     
     
       3. The security circuit of claim 1 wherein said programming means includes means for enabling the initialization of said security data to said first state, said initialization enabling means being disabled after the programmable logic device is packaged. 
     
     
       4. The security circuit of claim 3 wherein said enabling means comprises an extra wafer probe pad which is inaccessible after the programmable logic device is packaged. 
     
     
       5. The security circuit of claim 3 wherein said programming means further includes gating means responsive to said security data replica and said enabling means. 
     
     
       6. The security circuit of claim 1, wherein said disabling means comprises an address decoder. 
     
     
       7. The invention of claim 1 wherein said programming means further selectively and regeneratively erases said electrically erasable means when the programmable logic device is being programmed in the edit mode and when the security data is in said first stage. 
     
     
       8. The invention of claim 1 further comprising means for reading the state of said security data, said reading means being adapted to provide margin against high temperature charge loss effects. 
     
     
       9. A security circuit for preventing the erasure, programming, or interrogation of predetermined electrically erasable memory cells in an integrated circuit programmable logic device when such programmable logic device is in an edit mode wherein selected electrically erasable cells of the programmable logic can be erased, programmed, or interrogated, comprising: electrically erasable means for storing security data having first and second states;   programming means responsive to control signals and said security data for electrically erasing said electrically erasable means to initialize said security data to said first state and for programming said security data to said second state in a selected edit mode, said programming means being disabled from resetting said security data to said first state after said security data is programmed to said second state; and   means for disabling access to the predetermined electrically erasable memory cells in response to said second state of said security data when the programmable logic device is in the edit mode.   
     
     
       10. The security circuit of claim 9 wherein said electrically erasable means comprises a floating gate transistor. 
     
     
       11. The security circuit of claim 9 wherein said programming means includes means for enabling the initialization of said security data to said first state, said initialization enabling means being disabled after the programmable logic device is packaged. 
     
     
       12. The security circuit of claim 11 wherein said enabling means comprises an extra wafer probe pad which is inaccessible after the programmable logic device is packaged. 
     
     
       13. The security circuit of claim 11 wherein said programming means further includes gating means responsive to said security data and said enabling means. 
     
     
       14. The security circuit of claim 9 wherein said disabling means comprises an address decoder. 
     
     
       15. The invention of claim 9 wherein said programming means further selectively and regeneratively erases said electrically erasable means when the programmable logic device is being programmed in the edit mode and when the electrically erasable means is in said first state. 
     
     
       16. The invention of claim 9 further comprising means for reading the state of said security data, said reading means being adapted to provide margin against high temperature charge loss effects.