Error detection circuit

Abstract

An error detection circuit having a plurality of interconnected modules such as field replaceable units, each of the modules being driven by a system clock such that a failed module propagates errors to other modules before the system clock can be stopped. Each of the modules has at least one error checker circuit for generating an error checker signal when an error occurs. Each module includes an error trigger which is set responsive to the detection of an error checker signal, with each error trigger forming the stage of a counter whose count identifies the error trigger which was first set. The counter formed by the error triggers is preferably a Galois field counter which starts to count only upon the receipt of a non-zero impulse to any of its stages, and whose final count contains a unique value which identifies the source of the first non-zero impulse.

Having thus described my invention, what I claim as new and desire to secure by Letters Patent is: 
     
       1. In a system having a plurality of modules driven by a system clock, each of said modules having error checker means for generating an error checker signal when an error occurs, an error detection circuit comprising: error detection means for each of said modules, said error detection means generating an error signal responsive to said error checker signal;   error trigger means for each of said modules and having an input for receiving said error signal from a respective one of said error detection means and an output, said error trigger means sensing said corrected error signal from said error detection means; and   connection means connected to the outputs of said error trigger means for forming a counter, with each of said error trigger means forming a stage of said counter wherein the count of said counter indicates the first of said error trigger means to sense said error signal on its input.   
     
     
       2. The error detection circuit of claim 1 wherein each of said error trigger means includes a modulo two counter. 
     
     
       3. The error detection circuit of claim 1 wherein said connection means connects said plurality of error trigger means to form a Galois field counter. 
     
     
       4. The error detection circuit of claim 3 wherein each of said error detection means comprises: error reporting register means having a first input for receiving said error checker signal when an error has occurred, and an output for generating a local freeze signal responsive to said error checker signal;   local freeze logic means having an input connected to the output of said error reporting register means, said local freeze logic means for stopping said system clock responsive to said local freeze signal; and   a first OR gate having a first input connected to the output of said error reporting register means, a second input connected by said connecting means to the output of the error trigger means of the immediately preceding stage of said counter, and an output connected to the input of its respective error trigger means, said first OR gate generating said error signal responsive to either said local freeze signal from said error reporting register or a count signal from said immediately preceding stage.   
     
     
       5. The error detection circuit of claim 4 wherein said local freeze logic means has a second input, and wherein said connecting means comprises: a second OR gate having multiple inputs and an output, each of said multiple inputs being connected to the output of one of said error trigger means;   global freeze logic means having an input connected to the output of said second OR gate and an output, said global freeze logic means for generating a global freeze signal on its output responsive to said second OR gate; and   a global freeze conductor connected between the output of said global freeze logic means and the second input of each of said local freeze logic means, said global freeze conductor for transmitting said global freeze signal from said global freeze logic means to all of said local freeze logic means such that, responsive to said global freeze signal, error signals of said modules subsequent to said global freeze signal are not counted by said counter.   
     
     
       6. The error detection circuit of claim 5 wherein each of said local freeze logic means has an output for generating a freeze reporting signal responsive to either of said local freeze signal or said global freeze signal, and said error reporting register means has a second input connected to the output of said local freeze logic means and includes means for reporting the presence of said error checker signal and said freeze reporting signal on its first and second inputs, respectively. 
     
     
       7. The error detection circuit of claim 5 wherein said connecting means further comprises at least one Exclusive-OR gate having inputs connected to selected ones of the outputs of said error trigger means, and an output connected to the second input of at least one of said first OR gates such that the count of said Galois field counter counts in accordance with an irreducible polynomial in the GF(2**N); where N is chosen such that 2**N is equal to or greater than the number of cycles necessary for said system clock to be stopped by said global freeze logic means after the set of the first of said error trigger means by the detection of said error signal.   
     
     
       8. The error detection circuit of claim 7 further comprising a second Galois field counter having a plurality of stages, said global freeze conductor of said first Galois field counter being connected to one stage of said second Galois field counter such that said second Galois field counter indicates which group of several groups of modules detects a first error signal, and said first Galois field counter indicates which individual module of that group detects said first error signal.