BIPMOS decoder circuit

Abstract

A decoder incorporates the advantageous features of both bipolar and BICMOS decoding circuits through the use of BIPMOS technology. PMOS gating transistors are used to control the operation of bipolar output transistors. It is only necessary to operate the PMOS transistors with relatively small drain voltage variations, since the bipolar transistors are sensitive to such small variations. Further, transient signals are referenced to one power supply voltage only, to thereby make the logic swing and performance characteristics of the decoder independent of power supply voltage variations. Therefore it becomes possible to use PMOS transistors that have smaller voltage requirements than conventional CMOS circuits.

What is claimed is: 
     
       1. 1-of-N 2  decoder having N 2  output lines each of which carries a binary logic signal with a value that is referenced to only a single power source voltage, comprising: a pair of 1-of-N predecoders each having N control lines and being responsive to an input signal to produce a signal at one binary voltage level on one of said control lines and a signal at a complementary binary level on the other N-1 control lines;   N 2  p-channel MOS transistors each having a drain-source current path connected between said power source voltage and a current sink commonly connected to all of said MOS transistors through respective loads;   N 2  bipolar NPN transistors each having a collector connected to said power source voltage and an emitter connected to a current sink common to all of said bipolar transistors, the collector-emitter paths of said bipolar transistors being respectively connected to said N 2  output lines, each of said bipolar transistors having a base that is connected to the drain-source current path of a respective one of said MOS transistors; and   logic selection means connected to the gates of said MOS transistors and responsive to the binary signals on the control lines of said predecoders to cause one of said MOS transistors to conduct current along its drain-source current path and thereby actuate the bipolar transistor connected to said one MOS transistor so that said bipolar transistor conducts current and produces on the associated output line a binary signal having a predetermined voltage relative to said power source voltage.   
     
     
       2. The decoder of claim 1 wherein each predecoder comprises an input terminal for receiving a plural bit input signal, N selection gates each being logically connected to said input terminal such that only one of said gates is in a predetermined state at any time in response to the bits in said input signal, N level shifting circuits each including at least one bipolar transistor having a collector connected to a power supply voltage and being responsive to the state of a respective selection gate to produce an output voltage at an output emitter wherein said N control lines respectively produce output signals related to the output voltages at said output emitters of said level shifting circuits. 
     
     
       3. The decoder of claim 2 wherein each level shifting circuit includes plural diode-connected transistors connected in series between said bipolar transistor and said output lines. 
     
     
       4. The decoder of claim 2 further including a bipolar switching transistor having a base electrode receiving said output voltage of a level shifting circuit and a collector connected to an associated control line, and a pull-up resistor connected between said collector of said switching transistor and said power supply voltage. 
     
     
       5. The decoder of claim 4 wherein said pull-up resistor has a value such that the voltage at the collector of said switching transistor is greater than the voltage at the base of said switching transistor when the associated selection gate is in said predetermined state, to thereby prevent saturation of said switching transistor. 
     
     
       6. The decoder of claim 1 wherein said logic selection means includes a second P-channel MOS transistor in series with each of said N 2  MOS transistors, wherein a gate electrode of one of said series-connected MOS transistors is connected to a control line of one of said predecoders and the gate electrode of the other series connected MOS transistor is connected to a control line of the other predecoder. 
     
     
       7. The decoder of claim 1 wherein said logic selection means includes: a first tier of bipolar transistors having their emitters connected in common to a current source and each having a base electrode which receives a different respective binary signal from one of said predecoders, and   a plurality of second tiers of bipolar transistors each comprising plural bipolar transistors having their emitters connected in common to the collector of a respective one of the transistors in said first tier, the transistors in each of said second tier having base electrodes which receive respective binary signals from the other of said predecoders and collector electrodes which are connected to respective ones of said MOS transistors.   
     
     
       8. A 1-of-N 2  BIPMOS decoder circuit comprising: a predecoding circuit which receives an input signal and produces a logic output signal designating one of N possible output conditions indicated by said input signal;   N decoding gates respectively producing said N output conditions, each of said decoding gates including:   at least one p-channel MOS transistor having a gate electrode for receiving a binary logic signal resulting from the logic output signal of said predecoding circuit,   a bipolar output transistor having a base electrode connected to a drain of said MOS transistor such that said bipolar output transistor is rendered selectively conductive in response to the state of the binary logic signal at the gate electrode of said MOS transistor,   an output terminal connected to one of the collector and emitter of said bipolar transistor, and   a current sink connected in common to the drain of the MOS transistor in each of said N gates.   
     
     
       9. The decoder circuit of claim 8 wherein said decoding gate includes two p-channel MOS transistors having their source-drain current paths connected in series, with the source electrode of one of said MOS transistors being connected to a power supply voltage and the drain electrode of the other MOS transistor being connected to the base electrode of said bipolar output transistor. 
     
     
       10. The decoder circuit of claim 9 wherein each of said two MOS transistors has a gate electrode which receives a binary level logic signal from said predecoding circuit. 
     
     
       11. The decoder circuit of claim 9 wherein the collector of said bipolar output transistor is connected to said power supply voltage by means of a pull-up transistor, and said output terminal is connected to said collector. 
     
     
       12. The decoder circuit of claim 9 wherein the collector of said bipolar output transistor is directly connected to said power supply voltage, and said output terminal is connected to the emitter of said output transistor in an emitter follower relationship. 
     
     
       13. The decoder circuit of claim 8 further including a current sink connected in common to the emitter of the bipolar output transistor in each of said N gates. 
     
     
       14. The decoder circuit of claim 8 further including: a first tier of bipolar transistors having their emitters connected in common to a current source and each having a base electrode which receives a different respective binary signal from said predecoding circuit, and   a plurality of second tiers of bipolar transistors each comprising plural bipolar transistors having their emitters connected in common to the collector of a respective one of the transistors in said first tier, the transistors in each of said second tier having base electrodes which receive respective binary signals from said predecoding circuit and collector electrodes which are connected to the MOS transistor of respective ones of said N decoding gates.   
     
     
       15. The decoder circuit of claim 14 wherein all of said bipolar transistors are NPN transistors. 
     
     
       16. The decoder circuit of claim 8 wherein said predecoding circuit comprises K predecoders each having N 1/K  output lines, each predecoder receiving said input signal and being responsive thereto to produce a first predetermined voltage on one of said output lines and a second predetermined voltage on the other N 1/K  -1 output lines. 
     
     
       17. The decoder of claim 16 wherein each predecoder comprises an input terminal for receiving a plural bit input signal, multiple selection gates each being logically connected to said input terminal such that only one of said gates is in a predetermined state at any time in response to the bits in said input signal, multiple level shifting circuits each including at least one bipolar transistor having a collector connected to a power supply voltage and being responsive to the state of a respective selection gate to produce an output voltage at an output emitter and multiple lines respectively producing output signals related to the output voltages at said output emitters of said level shifting circuits. 
     
     
       18. The decoder circuit of claim 17 wherein each level shifting circuit includes plural diode-connected transistors connected in series between said bipolar transistor and said output lines. 
     
     
       19. The decoder circuit of claim 17 further including a bipolar switching transistor having a base electrode receiving said output voltage of a level shifting circuit and a collector connected to an associated output line, and a pull-up resistor connected between said collector of said switching transistor and said power supply voltage. 
     
     
       20. The decoder circuit of claim 19 wherein said pull-up resistor has a value such that the voltage at the collector of said switching transistor is greater than the voltage at the base of said switching transistor when the associated selection gate is in said predetermined state, to thereby prevent saturation of said switching transistor. 
     
     
       21. A decoder circuit comprising: a first plurality of predecoding means;   a second plurality of MOS logic gates, each fabricated using a single MOS process and comprising at least a first plurality of MOS transistors, receiving a first plurality of signals one from each said predecoding means, each said gate being connected to a first current sink, only one of said gates drawing a conduction-level current at any given time; and   a second plurality of bipolar transistor drives, each receiving a signal from a different one of said gates and driving a separate output line in dependence thereon, each said transistor being connected to a second current sink, only one of said transistors drawing an appreciable current at any given time.   
     
     
       22. The decoder circuit of claim 21 in which said decoder circuit is monolithically integrated. 
     
     
       23. The decoder circuit of claim 22 in which said MOS process is PMOS. 
     
     
       24. The decoder circuit of claim 23, in which said output lines are referenced to a single voltage reference. 
     
     
       25. The decoder circuit of claim 24 in which the collector of each said driver is connected to said single voltage reference, through a resistance, and to said output line. 
     
     
       26. The decoder circuit of claim 25 in which said first plurality of MOS transistors are connected in series with one another. 
     
     
       27. The decoder circuit of claim 26 in which said MOS transistors have a channel width less than that required to drive another MOS transistor.