Interface comprising message and protocol processors for interfacing digital data with a bus network

Abstract

A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.

What is claimed is: 
     
       1. A network interface equipment for interfacing digital data on a bus with a user equipment, comprising: a message processor;   a message random-access memory;   means in said message random-access memory for responding to data requests from said bus, said message processor and from said user equipment;   said message random-access memory including means for storing data portions of a data packet being transmitted or received;   a protocol processor;   a protocol random-access memory;   means in said protocol random-access memory for responding to protocol requests from said bus and said protocol processor;   said protocol processor including means for producing at least a header portion of said packet for storage in said protocol random-access memory for data packets to be transmitted and for testing correctness of received messages; and   said message random-access memory and said protocol random-access memory including means for responding to any of their respective data requests independently of the other.   
     
     
       2. A network interface equipment according to claim 1 further comprising a status random-access memory providing communication between said message processor and said protocol processor. 
     
     
       3. A network interface equipment according to claim 1 wherein said message random-access memory includes logic means for permitting a response to an earlier data request to said message random-access memory and for generating a wait signal in response to a later data request. 
     
     
       4. A network interface equipment according to claim 3 wherein said logic means includes means for selecting a one of two simultaneous requests according to a priority rule.