Digital signal processing circuit driven by a switched clock and used in television receiver for processing standard and nonstandard television signals

Abstract

A digital television receiver includes a decision circuit for deciding whether an input television signal is a standard signal or a nonstandard signal. A first clock signal generator circuit for generating a first sampling clock signal synchronized with a color burst signal is provided in combination with a second clock signal generator circuit for generating a second sampling clock signal synchronized with a horizontal synchronizing signal. When the standard television signal is received, the television signal is processed by employing the first sampling clock signal. When the nonstandard television signal is received, the television signal is processed by employing the second sampling clock signal.

We claim: 
     
       1. A signal processing circuit for use in a television receiver designed to receive a standard television signal which contains a picture signal, a chrominance subcarrier signal and a horizontal synchronizing signal and in which ratio between the frequency of said chrominance subcarrier signal and the frequency of said horizontal synchronizing signal is equal to a predetermined value, or   a nonstandard television signal which contains a picture signal, a chrominance subcarrier signal and a horizontal synchronizing signal and in which ratio between the frequency of said chrominance subcarrier signal and the frequency of said horizontal synchronizing signal differs from the corresponding ratio in said standard television signal, and including   analogue/digital converter means for converting said television signals into digital signals,   motion-adaptive signal processing circuit means for processing said television signals converted to said digital signals, and   digital/analogue converter means for converting said television signals processed by said motion-adaptive signal processing circuit means to analogue signals,   characterized in that said signal processing circuit comprises:   (a) an input terminal to which said standard television signal or said nonstandard television signal is supplied;   (b) luminance signal/chrominance signal separating circuit connected to said input terminal for receiving said standard television signal or said nonstandard television signal to separate a luminance signal and a chrominance signal from said standard television signal or said nonstandard television signal for thereby producing said luminance signal and two color difference signals, said luminance signal and said color difference signals being supplied to said analogue/digital converter means;   (c) burst signal extracting circuit means connected to said input terminal for receiving said standard television signal to extract a burst signal from said standard television signal or said nonstandard television signal;   (d) horizontal synchronizing signal separator circuit means connected to said input terminal for receiving said standard television signal or said nonstandard television signal to separate a horizontal synchronizing signal from said standard television signal or said nonstandard television signal;   (e) first clock signal generating circuit means connected to said burst signal extracting circuit means and including a first phase-locked loop for generating a first clock signal synchronized with said burst signal;   (f) second clock signal generating circuit means connected to said horizontal synchronizing signal separating circuit and including a second phase-locked loop for generating a second clock signal synchronized with said horizontal synchronizing signal;   (g) signal decision circuit means connected to said first and second clock generating circuit means for comparing phase of said first clock signal with that of said second clock signal to thereby produce a coincidence output signal when frequencies of said first and second clock signals lie within a predetermined range while producing a discrepancy output signal when the frequencies of said first and second clock signals are out of said predetermined range; and   (h) switch circuit means connected to said analogue/digital converter means, said digital/analogue converter means, and said first and second clock signal generating circuit means and controlled by said decision circuit means such that upon reception of the coincidence signal from said decision circuit means, said switch circuit means supplies said first clock signal received from said first clock signal generating circuit to said analogue/digital converter means and said digital/analogue converter means while upon reception of said discrepancy signal from said signal decision circuit, said switch circuit means supplies said second clock signal supplied from said second clock signal generating circuit means to said analogue/digital converter circuit means and said digital/analogue converter means.   
     
     
       2. A signal processing circuit for a television receiver according to claim 1, wherein said first phase-locked loop of said first clock signal generating means includes: (a) a first phase comparison circuit connected to said burst extracting circuit means and supplied with the burst signal from said burst extracting circuit means;   (b) a first low-pass filter connected to said first phase comparison circuitry;   (c) a first voltage controlled oscillator connected to said first low-pass filter and supplied with a control voltage from said first low-pass filter for generating the first clock signal; and   (d) a first frequency division circuitry connected between said first voltage controlled oscillator and said first phase comparison circuitry for dividing frequency of the first clock signal generated by said voltage controlled oscillator, wherein the signal resulting from said frequency division is supplied to said first phase comparison circuitry.   
     
     
       3. A signal processing circuit for a television receiver according to claim 2, further including: (a) a disturbance detecting circuitry connected to said first clock signal generating circuit means for detecting the control voltage supplied to said first voltage controlled oscillator of said first phase-locked loop circuit to produce an output signal when said control voltage exceeds a predetermined threshold value, and   (b) a logical sum circuitry connected to said disturbance detecting circuitry and said signal decision circuit means for supplying the output signal of said disturbance detecting circuitry to said switch circuit means as the discrepancy signal.   
     
     
       4. A signal processing circuit for a television receiver according to claim 2, wherein the first voltage controlled oscillator produces the first clock signal having a frequency eight times as high as the frequency of the chrominance subcarrier signal, said first frequency divider dividing the frequency of said first clock signal by a divisor of 8 (multiplication with 1/8). 
     
     
       5. A signal processing circuit for a television receiver according to claim 1, wherein said signal decision circuit means includes: (a) a second frequency division circuitry connected to said first clock signal generating circuit means to be supplied therefrom with the first clock signal after having undergone a frequency division for further dividing frequency of said first clock signal undergone said frequency division;   (b) a third frequency division circuitry connected to said second clock generating circuit means to be supplied with the second clock signal after having undergone a frequency division for further dividing frequency of said second clock signal undergone said frequency division;   (c) a first comparator connected to said second and third frequency division circuitries for comparing the frequencies outputted by said second and third frequency division circuitries to produce said coincidence signal or said discrepancy signal; and   (d) an integrator connected to said first comparator for integrating said coincidence signal and said discrepancy signal.   
     
     
       6. A signal processing circuit for a television receiver according to claim 5, wherein said integrator includes: (a) an up-down counter connected to said first comparator to be supplied therefrom with the coincidence signal and the discrepancy signal for counting up and down said coincidence signal sand said discrepancy signal; and   (b) a set-reset flip-flop connected to said up-down counter to be set in response to a first output signal of said up-down counter while being reset in response to a second output signal of said up-down counter.   
     
     
       7. A signal processing circuit for a television receiver according to claim 5, wherein said second frequency division circuitry is connected to said third frequency division circuitry such that said second frequency division circuit is reset by the output signal of said third frequency division circuit. 
     
     
       8. A signal processing circuit for a television receiver according to claim 1, wherein the second phase-locked loop circuit of said second clock signal generating circuit means includes: (a) a second phase comparison circuitry connected to said horizontal synchronizing separator circuit means to be supplied therefrom with a horizontal synchronizing signal;   (b) a second low-pass filter connected to said second phase comparison circuitry;   (c) a second voltage controlled oscillator connected to said second low-pass filter to be supplied therefrom with a control voltage for generating the second clock signal; and   (d) a fourth frequency division circuitry connected between said second voltage controlled oscillator and said second phase comparison circuitry for dividing frequency of the second clock signal.   
     
     
       9. A signal processing circuit for use in a television receiver designed to receive a standard television signal which contains a picture signal, a chrominance subcarrier signal and a horizontal synchronizing signal and in which ratio between the frequency of said chrominance subcarrier signal and the frequency of said horizontal synchronizing signal is equal to a predetermined value, or   a nonstandard television signal which contains a picture signal, a chrominance subcarrier signal and a horizontal synchronizing signal and in which ratio between the frequency of said chrominance subcarrier signal and the frequency of said horizontal synchronizing signal differs from the corresponding ratio in said standard television signal, and including   analogue/digital converter means for converting said television signals into digital signals,   motion-adaptive signal processing circuit means for processing said television signals converted to said digital signals, and   digital/analogue converter means for converting said television signals processed by said motion-adaptive signal processing circuit means to analogue signals,   characterized in that said signal processing circuit comprises:   (a) an input terminal to which said standard television signal or said nonstandard television signal is supplied;   (b) luminance signal/chrominance signal separating circuit connected to said input terminal for receiving said standard television signal or said nonstandard television signal to separate a luminance signal and a chrominance signal from said standard television signal or said nonstandard television signal for thereby producing said luminance signal and two color difference signals;   (c) burst signal extracting circuit means connected to said input terminal for receiving said standard television signal to extract a burst signal from said standard television signal or said nonstandard television signal;   (d) horizontal synchronizing signal separator circuit means connected to said input terminal for receiving said standard television signal or said nonstandard television signal to separate a horizontal synchronizing signal from said standard television signal or said nonstandard television signal;   (e) first clock signal generating circuit means connected to said burst signal extracting circuit means and including a first phase? locked loop for generating a first clock signal synchronized with said burst signal;   (f) second clock signal generating circuit means connected to said horizontal synchronizing signal separating circuit and including a second phase-locked loop for generating a second clock signal synchronized with said horizontal synchronizing signal;   (g) horizontal synchronizing circuit means connected to said horizontal synchronizing signal separating circuit and including a second phase-locked loop for generating a reference signal synchronized with said horizontal synchronizing signal;   (h) signal decision circuit means connected to said first clock generating circuit means for comparing phase of said first clock signal with that of said reference signal to thereby produce a coincidence output signal when the frequency of said first clock signal lies within a predetermined range while producing a discrepancy output signal when the frequency of said first clock signal is outside of said predetermined range; and   (i) switch circuit means connected to said analogue/digital converter means, said digital/analogue converter means, and said first and second clock signal generating circuit means and controlled by said decision circuit means such that upon reception of the coincidence signal from said decision circuit means, said switch circuit means supplies said first clock signal received from said first clock signal generating circuit to said analogue/digital converter means and said digital/analogue converter means while upon reception of said discrepancy signal from said signal decision circuit, said switch circuit means supplies said second clock signal supplied from said second clock signal generating circuit means to said analogue/digital converter circuit means and said digital/analogue converter means.   
     
     
       10. A signal processing circuit for a television receiver according to claim 9, wherein said first phase-locked loop of said first clock signal generating means includes: (a) a phase comparison circuitry connected to said burst extracting circuit means and supplied with the burst signal from said burst extracting circuit means;   (b) a low-pass filter connected to said first phase comparison circuitry;   (c) a voltage controlled oscillator connected to said first low-pass filter and supplied with a control voltage from said first low-pass filter for generating the first clock signal; and   (d) a frequency division circuitry connected between said first voltage controlled oscillator and said phase comparison circuitry for dividing the frequency of the first clock signal generated by said voltage controlled oscillator, wherein the signal resulting from said frequency division is supplied to said phase comparison circuitry.   
     
     
       11. A signal processing circuit for a television receiver according to claim 10, further including (a) a disturbance detecting circuitry connected to said first clock signal generating circuit means for detecting the control voltage supplied to said first voltage controlled oscillator of said first phase-locked loop circuit to produce an output signal when said control voltage exceeds a predetermined threshold value, and   (b) a logical sum circuitry connected to said disturbance detecting circuitry and said signal decision circuit means for supplying the output signal of said disturbance detecting circuitry to said switch circuit means as the discrepancy signal.   
     
     
       12. A signal processing circuit for a television receiver according to claim 10, wherein said first voltage controlled oscillator produces the first clock signal having a frequency eight times as high as the frequency of the chrominance subcarrier signal, said first frequency divider dividing the frequency of said first clock signal by a divisor of 8 (multiplication with 1/8). 
     
     
       13. A signal processing circuit for a television receiver according to claim 9, wherein said signal decision circuit means includes: (a) a second frequency division circuitry connected to said first clock signal generating circuit means to be supplied therefrom with the first clock signal after having undergone a frequency division for further dividing the frequency of said first clock signal having undergone said frequency division;   (b) a third frequency division circuitry connected to said horizontal synchronizing circuit means to be supplied with the reference signal after having undergone a frequency division for further dividing the frequency of said reference signal having undergone said frequency division;   (c) a first comparator connected to said second and third frequency division circuitires for comparing the frequencies outputted by said second and third frequency division circuitires to produce said coincidence signal or said discrepancy signal; and   (d) an integrator connected to said first comparator for integrating said coincidence signal or said discrepancy signal.   
     
     
       14. A signal processing circuit for a television receiver according to claim 13, wherein said integrator includes: (a) an up-down counter connected to said comparator to be supplied therefrom with the coincidence signal and the discrepancy signal for counting up and down said coincidence signal and said discrepancy signal; and   (b) a set-reset flip-flop connected to said up-down counter to be set in response to a first output signal of said up-down counter while being reset in response to a second output signal of said up-down counter.   
     
     
       15. A signal processing circuit for a television receiver according to claim 13, wherein said disturbance detecting circuit includes: (a) an amplifier circuitry connected to said first low-pass filter to be supplied with the control voltage produced by said first low-pass filter as the output signal thereof for amplifying said control voltage;   (b) a second comparator connected to said amplifier circuitry for producing an output signal when said amplified control voltage exceeds a predetermined voltage value; and   (c) a set-reset flip-flop connected between said second comparator and said third frequency division circuitry so as to be set in response to the output signal of said second comparator while being reset in response to the output signal of said third frequency division circuitry.   
     
     
       16. A signal processing circuit for a television receiver according to claim 13, wherein said second frequency division circuitry is connected to said third frequency division circuitry such that said second frequency division circuit is reset by the output signal of said third frequency division circuit.