Variable gain encoder apparatus and method

Abstract

A variable gain analog to digital compression encoder apparatus and method is operational for `on the fly` gain adjustments without introducing significant distortion or noise in telephone conversation. An incoming analog signal is fixed gain reproduced as a first stabilized mid-operating point analog signal. A second stabilized mid-operating point analog signal is produced in inverse proportion to the first stabilized mid-operating point analog signal, in response to a signal tapped along a signal division of a difference between the first and second signals. The second signal is compression encoded at a predetermined rate to produce pulse code modulated signal samples. The tap may be varied to change the encoding gain, at any time, in accordance with operating requirements of a telephone apparatus.

We claim: 
     
       1. A gain controllable analog to digital (A/D) encoder for providing digital words being representative of samples of an input analog signal, comprising: an analog to digital converter circuit for generating said digital words each consisting of plural bits, including a sign bit;   a first means for generating a fixed gain analog signal in response to the input analog signal, the first means being mid-operating point stabilized in response to the sign bits corresponding to the fixed gain analog signal; and   a second means for supplying a variably controlled gain analog signal to the converter circuit in response to the stabilized mid-operating point fixed gain analog signal from the first means, the variably controlled gain analog signal from the second means being mid-operating point stabilized in response to the sign bits of the digital words.   
     
     
       2. An A/D encoder as defined in claim 1 wherein the variably controlled gain analog signal is supplied to the converter circuit from the second means in inverse relationship to the fixed gain analog signal generated by the first means. 
     
     
       3. An A/D encoder as defined in claim 1 wherein the second means is responsive to an externally supplied control signal for defining an amount of amplification in the second 
     
     
       4. An A/D encoder as defined in claim 3 wherein the externally supplied control signal is a plural bit binary word. 
     
     
       5. An A/D encoder as defined in claim 1 wherein the A/D converter circuit is a compression A/D converter circuit. 
     
     
       6. A gain controllable analog to digital (A/D) encoder for providing digital words being representative of samples of an input analog signal, comprising: an analog to digital converter circuit for generating said digital words each consisting of plural bits, including a sign bit;   a first means for generating a fixed gain analog signal in response to the input analog signal, the first means being mid-operating point stabilized in response to the sign bits corresponding to the fixed gain analog signal;   a second means for supplying a variably controlled gain analog signal to the converter circuit in response to and in inverse relationship to the stabilized mid-operating point fixed gain analog signal from the first means, the signal from the second means being midoperating point stabilized in response to inverted sign bits of the digital words; and   invertor means for inverting the sign bits of said digital words to provide said inverted sign bits.   
     
     
       7. A gain controlled A/D encoder as defined in claim 1 further comprising: switches means for alternately coupling the fixed gain analog signal from the first means, and the variabaly controlled gain analog signal from the second means to the converter circuit at a fixed rate being at least twice that of a Niquist frequency; and   wherein the converter circuit is operated at said fixed rate, whereby encoded samples of the signals from the first and second means are alternately available at an output of the converter circuit.   
     
     
       8. A gain controllable analog to digital (A/D) encoder for providing digital words being representative of samples of an input analog signal, comprising; an analog to digital converter circuit for generating said digital words each consisting of plural bits, including a sign bit;   a first means for generating a fixed gain analog signal at an output thereof in response to the input analog signal, the first means being mid-operating point stabilized in response to the sign bits corresponding to the fixed gain analog signal;   a second means having an output and an input, the record means for supplying a variably controlled gain analog signal to the converter circuit in response to the stabilized mid-operating point fixed gain analog signal from the first means, the variably controlled gain analog signal from the second means being mid-operating point stabilized in response to the sign bits of the digital words; and   a voltage divider being connected between the outputs of the first and second means and including at least two voltage tap positions being selectively connectable to the input of the record means for coupling the analog signal from the first means thereto.   
     
     
       9. A gain controllable analog to digital (A/D) encoder for providing digital words being representative of samples of an input analog signal, comprising: an analog to digital converter circuit for generating said digital words each consisting of plural bits, including a sign bit;   a first means for generating a fixed gain analog signal in response to the input analog signal, the first means being mid-operating point stabilized in response to the sign bits corresponding to the fixed gain analog signal; and   a second means for supplying a variably controlled gain analog signal to the converter circuit in response to the stabilized mid-operating point fixed gain analog signal from the first means, the variably controlled gain analog signal from the second means being mid-operating point stabilized in response to the sign bits of the digital words;   the second means comprising:   a differential amplifier having an output for supplying said controlled gain analog signal and an inverting input; and   a voltage divider being connected between the output of the first means and the output of the differential amplifier, and including a plurality of voltage tapable positions, one of which being connected to the inverting input.   
     
     
       10. An A/D encoder as defined in claim 9 wherein the voltage divider comprises a plurality of resistance segments and a plurality of corresponding switch means being connected between each of the segments and the inverting input. 
     
     
       11. An A/D encoder as defined in claim 10 wherein each of said switch means consists of a column of field effect transistor devices being connected row on row in common with corresponding gate control leads, the field effect transistor devices being arranged in opposite responsive combinations and being selectively bridged, such that a binary word being applied to said control leads causes one column to be of a much higher conductance than any of the other columns. 
     
     
       12. An A/D encoder as defined in claim 9 wherein the voltage divider is responsive in operation to n bit binary words, and comprises: n leads for application of the binary words thereto, each of the n leads being connected to control 2 n  switching devices, each of the 2 n  switching devices being arranged in a corresponding column of at least n switching devices, each of said columns being connected between a common rail and a corresponding voltage tap of a segmented resistance rail having 2 n  resistance segments connected in series between the output of the first means and the output of the differential amplifier in the second means, said common rail being connected to the inverting input of the differential amplifier.   
     
     
       13. A gain controllable analog to digital (A/D) encoder for providing digital words being representative of samples of an input analog signal, comprising: an analog to digital converter circuit for generating said digital words each consisting of plural bits, including a sign bit; a first means for generating a fixed gain analog signal in response to the input analog signal, the first means being mid-operating point stabilized in response to the sign bits corresponding to the fixed gain analog signal; and   a second means for supplying a variably controlled gain analog signal to the converter circuit in response to the stabilized mid-operating point fixed gain analog signal from the first means, the variably controlled gain analog signal from the second means being mid-operating point stabilized in response to the sign bits of the digital words; and   one of the first and second means including an invertor being responsive to the sign bits of each of said digital words to provide said sign bits corresponding to the fixed gain analog signal.   
     
     
       14. An alterable gain method for generating digital word representations of an analog signal, comprising the steps of (a) stabilized mid-operating point amplifying at a predetermined fixed gain to provide a first signal in response to the analog signal and first sign bits correspond thereto;   (b) stabilized mid-operating point amplifying at a controllably varied gain to provide a second signal in response to the first signal and second sign bits corresponding to the second signal; and   (c) analog to digital converting the first signal to provide at least the first sign bits and analog to digital converting the second signal to provide plural bit words each including one of said second sign bits, whereby said plural bit words are gain variable with respect to the first signal.   
     
     
       15. An alterable gain method for generating digital word representation of an analog signal as defined in claim 14 wherein the second signal is provided in inverse relationship to the first signal by inverse amplifying the first signal. 
     
     
       16. An alterable gain method for generating digital word representation of an analog signal as defined in claim 14 wherein the first signal is amplified with a gain being in accordance with an externally supplied control signal. 
     
     
       17. An alterable gain method for generating digital word representation of an analog signal as defined in claim 16 wherein the externally supplied control signal is a plural bit binary word. 
     
     
       18. An analog to digital encoder for providing plural digital words each word including a sign bit and being representative of samples of an input analog signal in a plurality of selectable gain relationships comprising; analog to digital converter means for generating the digital words at a rate in excess of at least twice a Niquist frequency;   first and second sign bit paths;   switch means having first and second input terminals and being operable at said rate for alternately coupling an input of the analog to digital converter means for receiving first and second analog signals, and having first and second output means for alternately coupling sign bits corresponding to the first and second analog signals to first and second sign bit paths respectively;   a first amplifier circuit including an operational amplifier in a fixed gain non-inverting configuration including an input for receiving the analog signal and a node for receiving a mid-operating point bias potential and an output for providing the first signal being a fixed gain reproduction of the analog signal;   a second amplifier circuit including an operational amplifier including a node common with a non-inverting input of the operational amplifier for receiving a mid-point bias potential, an inverting input, and, an output for providing the second signal being a variable gain inverted reproduction of the first signal;   a low pass filter means having a frequency cut off characteristic being less than the Niquist frequency, and being connected between the output of the first amplifier circuit and the first input terminal of the switch means;   the first sign bit path being connected to the node of the first amplifier circuit and including means for generating the bias potential in response to polarities of occurrences of the first sign bits;   the second sign bit path being connected to the node of the second amplifier circuit and including means for generating the bias potential in response to polarities of occurrences of the second sign bits;   a resistance means being connected between a first junction of the low pass filter and the first input terminal, and a second junction of the output of the operational amplifier in the second amplifier circuit and the second terminal, the resistance means including a tap means being variable between at least two positions, the tap means being connected to the inverting input of the operational amplifier in the second amplifier means.