Alternate memory addressing for information storage and retrieval

Abstract

An apparatus for alternate memory addressing of a random access memory (RAM) allows a first processor to write into the memory on a row-by-row basis and a second processor to read out of the memory on a column-by-column basis. The memory is typically divided into a pluralilty of channels into which the first processor writes data for respective channels asynchronously by the use of twin RAMs. While one RAM is written to by the first processor, the second RAM is read from synchronously with automatic address translation.

We claim: 
     
       1. An apparatus for the alternate addressing of a common memory system for storing and retrieval of digitized information comprising: first processor means connected to said memory system for writing said digitized information to said memory system, said digitized information written to said memory system being organized as a plurality of channels on a row-by-row basis in said memory system;   second processor means connected to said memory system for reading from said memory system said digitized information in defined segments as a plurality of frames from each of said plurality of channels on a column-by-column basis in said memory system; and   switching means for selectively connecting said first and second processor means to different address spaces of said memory system, said first and second processor means having simultaneous access to said memory system.   
     
     
       2. The apparatus recited in claim 1 wherein said switching means comprises multiplexer means responsive to said first processor means for selectively connecting said first and second processor means to said different address spaces, said multiplexer means including first address register means for addressing said different address spaces, said apparatus further comprising: second address register means in said first processor means connected to third address register means in said multiplexer means for transferring an address from said first processor means to said multiplexer means; and   fourth address register means in said second processor means connected to fifth address register means in said multiplexer means for transferring an address from said second processor means to said multiplexer means;   said multiplexer means further transferring an address from one of said third or fifth address register means to said first address register means to address said different address spaces of said memory system.   
     
     
       3. The apparatus recited in claim 2 further comprising address rearranging means connected to said fifth address register means for rearranging the address transferred from said fourth address register means to said fifth address register means. 
     
     
       4. The apparatus recited in claim 1 wherein said memory system includes twin random access memory means, said switching means alternately connecting said first processor means to a first of said memory means and then to a second of said memory means while alternately connecting said second processor means to said second memory means and then to said first memory means. 
     
     
       5. The apparatus recited in claim 4 wherein said switching means comprises first and second multiplexer means responsive to said first processor means for alternately connecting said first and second processor means to said first and second memory means, said first multiplexer means including first address register means for addressing said different address spaces of said first memory means and said second multiplexer means including second address register means for addressing said different address spaces of said second memory means, said apparatus further comprising: third address register means in said first processor means connected too fourth address register means in said switching means for transferring an address from said first processor means to said switching means; and   fifth address register means in said second processor means connected to sixth address register means in said switching means for transferring an address from said second processor means to said switching means;   said switching means further alternately transferring an address from one of said fourth or sixth address register means to said first address register means to address different address spaces of said first memory means and alternately transferring and address from one of said sixth or fourth address register means to said second address register means to address different address spaces of said second memory means.   
     
     
       6. The apparatus recited in claim 5 further comprising address rearranging means connected to said sixth address register means for rearranging the address transferred from said fifth address register means to said sixth address register means. 
     
     
       7. The apparatus recited in claim 6 wherein said segments are 2-byte words. 
     
     
       8. The apparatus recited in claim 7 wherein said second processor includes address means for reordering said 2-byte words by interchanging high order and low order bytes on odd addresses.