Triple-implanted drain in transistor made by oxide sidewall-spacer method

Abstract

A transistor for VLSI devices made by the sidewall-spacer method uses a reach-through implant both before and after the sidewall spacer is defined. An arsenic implant self-aligned with the gate prior to the sidewall oxide, then a phosphorus implant and lateral diffusion performed after the sidewall oxide etch creates a reduced impurity concentration and graded junction for the reach-through implanted region beneath the oxide sidewall spacer. An arsenic implant after the sidewall spacer is in place provides heavily-doped low-resistance source/drain regions.

What is claimed: 
     
       1. A field-effect transistor comprising a gate on a face of a semiconductor body, a channel beneath the gate, a heavily-doped drain region in said face spaced from the channel, first and second lightly-doped regions in the gap between the drain region and the channel, and a sidewall-spacer oxide segment above said gap, the impurity in said heavily-doped region being at a much higher doping level and diffused into the semiconductor body to a much lesser extent than the impurity in said lightly-doped regions, the impurities of the first and second regions being of differing diffusion coefficient and doping level providing a graded junction. 
     
     
       2. A device according to claim 1 in which the semiconductor body is P type silicon, the impurity in the heavily-doped region is arsenic, and the impurity in the lightly-doped regions are arsenic and phosphorous, to provide an N-channel transistor.