Arrangement for monitoring a computer system having two processors in a motor vehicle

Abstract

The invention is directed to an arrangement for monitoring a computer system with two processors in a motor vehicle. The arrangement provides that the two processors monitor each other to the same extent and that this monitoring occurs in the form of a hand-shake operation in the context of a cyclical data exchange between both processors. In this connection, it is especially advantageous that both processors: can operate fully independently of each other; need not utilize a directly coupled or common I/O-bus; and, are mutually asynchronously operable with different clock frequencies. The arrangement provides a mutual monitoring of two processors to the same extent so that a failure can be localized when it occurs. In this way, the arrangement can distinguish whether a processor has failed or whether an error is present in the peripheral hardware of the processors. For this purpose, the above-mentioned cyclical data exchange between both processors is utilized as an acknowledgement path for the monitoring function.

What is claimed is: 
     
       1. An arrangement for monitoring a computer system with two equal access processors in a motor vehicle, the arrangement comprising: data and control lines interconnecting said two processors with each other;   means for operating said processors independently of each other except for a cyclical data and command exchange via said data and control lines;   each of said processors having a dedicated first output for supplying a dynamic watch-dog signal;   each of said processors having a dedicated first input for identifying a static watch-dog signal;   each of said processors having a dedicated second output for supplying a software-reset signal;   said processors having respective reset inputs;   two logic OR-circuits, each of said OR-circuits having an output connected to the reset input of the processor corresponding thereto;   each of said OR-circuits having first and second inputs;   means for applying a start pulse in common to the first inputs of each of said OR-circuits;   two pump circuits corresponding to respective ones of said processors, each of said pump circuits having an input connected to the first output of the processor corresponding thereto and an output connected to the first input of the other one of the processors from which a static watch-dog signal can be taken in dependence upon an applied dynamic watch-dog signal;   two logic AND-circuits, each of said AND-circuits having a first input connected to the second output of the processor corresponding thereto;   each of said AND-circuits having a second input connected to the output of the pump circuit corresponding to the same processor as said AND-circuit for receiving the static watch-dog signal of the pump circuit; and,   each of said AND-circuits having an output connected to the second input of the OR-circuit corresponding to the other processor.   
     
     
       2. The arrangement of claim 1, wherein said processors are operated at different clock frequencies different from each other. 
     
     
       3. The arrangement of claim 1, wherein check words issued via said control lines are different for the data transmission on the data lines in dependence upon direction. 
     
     
       4. The arrangement of claim 1, wherein one of said processors is a master and operable with priority and the other one of said processors is a slave and subordinately operable so long as no defect is present and, when a defect is detected, each of the two processors processes essentially the same emergency function with the same capacity.