Semiconductor integrated-circuit apparatus

Abstract

A semiconductor integrated-circuit apparatus includes a electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality of bias cells which are common to the plurality of internal cells and which generate a predetermined voltage. A plurality of bias buffer circuits supply the predetermined voltage generated in the bias cells to the internal cells.

We claim: 
     
       1. An integrated circuit device formed on a substrate having a conduction layer formed therein, comprising: a first power supply line formed on said substrate;   a second power supply line formed on said substrate having a voltage different from a voltage of said first power supply line;   a plurality of ECL gate cells formed on said substrate, each of said ECL gate cells comprising: a pair of emitter coupled transistors having a base, having an emitter and having a collector, the collector of said emitter coupled transistors being operatively connected to said first power supply line;   a current source means, connected between the emitters of said emitter coupled transistors and said second power supply line; and   an output transistor having a base operatively connected to the collector of said emitter coupled transistors, having an emitter, and having a collector operatively connected to said first power supply line;     a plurality of input-output pads formed on said substrate and selectively connected to the base of one of said emitter coupled transistors and to the emitter of said output transistor through the conduction layer formed on the substrate; and   a plurality of electrostatic preventing means formed on the substrate and adjacent to said input-output pads respectively, each of said electrostatic preventing means including an electrostatic preventing element and a resistor, said electrostatic preventing means connected to one of said input-output pads such that when one of said input-output pads is connected to the base of one of said emitter coupled transistors said electrostatic preventing element is connected between one of said input-output pads and said first power supply line and said resistor is connected between one of said input-output pads and the base of one of said emitter coupled transistors, and when one of said input-output pads is connected to the emitter of said output transistor said electrostatic preventing element is connected between said one of said input-output pads and said first power supply line, the emitter of said output transistor being connected to said one of said input-output pads and said resistor not connected to said one of said input-output pads.   
     
     
       2. An integrated circuit device according to claim 1, wherein said electrostatic preventing element comprises a diode. 
     
     
       3. An integrated circuit device according to claim 1, wherein said electrostatic preventing element comprises a transistor.