Computational network

Abstract

A new associative computation network that is capable of storing multi-bit vectors includes a decision network and a feedback arrangement that, functionally, is separable into serially connected networks. The first network has its inputs connectd to the outputs of the decision network and is arranged to develop sets of excitatory and inhibitory drive signals. Each set corresponds to a stored vecor. For each different output state of the decision network, a different one of the drive signal sets appears at the output of the first network. The output leads of the first network, which may also be employed as the input interface leads, are connected to the second network. The second network develops output signals, applied to inputs of the decision network, which are proportional to the projection of the input signals applied to the second network on the stored vectors.

What is claimed is: 
     
       1. A network for storing K vectors M i , where i is an index in the range 1 to K designates a particular vector, and each vector M i  has components M ij  where j is an index in the range 1 to L designates the component number of the vector, K and L being integers, comprising: a decision network for developing at output ports of said decision network signals that indicate recognition of a degree of presence of said vectors within input signals appearing at input ports of said decision network; and   an interconnection network having K input leads connected to said output ports and output leads connected to said input ports, and L network interface leads, where each of said network interface leads, i, is connected to each output lead of said interconnection network, j, through a connection C ij  and to each input lead of said interconnection network j, through a connection C' ij , and where said C ij  and C' ij  connnections are related only to components j of vector i from among said K vectors.   
     
     
       2. The network of claim 1 wherein said C ij  connections develop signals at said input ports of said decision network that are related to the projections of signals on said network interface leads on said K vectors. 
     
     
       3. The network of claim 1 wherein each set of said C ij  connections for a selected value of j develop a signal at a j th  output lead of said interconnection network that is related to the projection of signals on said network interface leads on one of said K vectors. 
     
     
       4. The network of claim 1 wherein said C' ij  connections develop signals for driving said interconnection network to a state where signals on said network interface leads correspond to one of said K vectors. 
     
     
       5. The network of claim 1 wherein said decision network is a K-flop network and each set of said C' ij  connections for a given subscript j is related to one of said K vectors. 
     
     
       6. The network of claim 5 wherein each set of said C ij  connections develops signals at said input ports of said K-flop network that are related to the projections of said signals at said network interface leads on said K vectors. 
     
     
       7. The network of claim 5 wherein each vector M j  of said K vectors comprises bits M ij , and each of said C' ij  forms an excitatory connection when M ij  =1 and an inhibitory connection when M ij  =0. 
     
     
       8. The network of claim 5 wherein each vector M j  of said K vectors comprises bits M ij  and wherein C ij  =AND(V j ,M ij ), where V j  is a signal on a j th  lead of said network interface leads. 
     
     
       9. The network of claim 5 wherein each vector M j  of said K vectors comprises bits M ij  and wherein C ij  =EXNOR(V j ,M ij ), where V j  is a signal on a j th  lead of said network interface leads. 
     
     
       10. The network of claim 5 wherein each vector M j  of said K vectors comprises bits M ij , and wherein C' ij  =AND(E j ,M ij ), where E j  is a j th  output of said K-flop. 
     
     
       11. A network for storing K vectors comprising: a decision network having input ports and output ports for developing an output signal at said output ports indicative of the input port with the largest signal; and   an interconnection network having input leads connected to said output ports, output leads connected to said input ports, and network interface leads, where each of said network interface leads, i, is connected to each output lead of said interconnection network, j, through a connection C ij  and to each input lead of said interconnection network, j, through a connection C' ij , and where said C ij  and C' ij  connections associated with each lead j is related only to a chosen one of said K vectors.   
     
     
       12. A network for storing K vectors where each vector M i  includes bits M ij , comprising: a decision network having K input ports and K output ports for developing an output signal at said output ports indicative of the input port with a largest signal; and   an interconnection network having K input leads connected to said K output ports, K output leads connected to said K input ports, N network input leads, and N vector output leads, where each of said vector output leads, i, is connected to each output lead of said interconnection network, j, through a connection C ij , each corresponding network input lead, i, is connected to each input lead of said interconnection network, j, through a connection C' ij , and said C ij  and C' ij  connections are related to said K vectors.   
     
     
       13. The network of claim 12 wherein said decision network is a K-flop network and each of said C ij  and C' ij  connections is related to said M ij . 
     
     
       14. The network of claim 13 further comprising amplifiers interposed between said interconnection network input leads and said interconnection network vector output leads. 
     
     
       15. The network of claim 13 further comprising N amplifiers, each having an input lead connected to one of said network input leads and an output lead connected to said corresponding one of said interconnection network vector output leads. 
     
     
       16. A network sensitive to K vectors, each describable by N bits, comprising: an input port including N input leads for accepting applied input signals;   an amplification network responsive to said N input leads, for developing N output signals;   a template projection network responsive to said N output signals for developing K projection signals, each indicative of the projection of said N output signals on a different one of said K vectors;   a decision network responsive to said K projection signals for developing K drive signals indicative of the largest of said K projection signals; and   a template generator network responsive to said K drive signals for developing N template generation signals, applied to said N input leads, for driving said N output signals to a state corresponding to one of said K vectors.   
     
     
       17. A network for storing K vectors of N bits each where each vector M j  with j assuming values from 1 to K, includes bits M ij , with i assuming values from 1 to N, comprising: K amplifiers having input ports and output ports;   a feedback network having K output leads connected to said input ports of said amplifiers and K input leads connected to said output ports of said amplifiers, with each input lead, i, of said feedback network connected within said feedback network to each output lead, j, of said feedback network through an inhibitory connection of a first fixed value for all i≠j; and   an interconnection network having K input leads connected to said output ports of said amplifiers, K output leads connected to said input ports of said amplifiers, and N network interface leads, where each interface lead, i, is connected to each output lead of said interconnection network, j, through a connection C ij , and to each input lead of said interconnection network, j, through a connection C' ij , and where both said C ij  and C' ij  connections are related to said M ij .   
     
     
       18. The network of claim 17, further including control means for disabling said K amplifiers. 
     
     
       19. The network of claim 1 further comprising control means connected to said decision network for disabling all output signals at said output ports. 
     
     
       20. The network of claim 1, developing output signals responsive to signals appearing at said output ports of said decision network. 
     
     
       21. The network of claim 1 further comprising a network output port and shift register means interposed between said network output port and said output ports of said decision network. 
     
     
       22. The network of claim 21 further comprising encoding means interposed between said shift register means and said output ports of said decision network. 
     
     
       23. The network of claim 1 further comprising a network output port and encoder means interposed between said network output port and said output ports of said decision network. 
     
     
       24. The network of claim 12 further comprising network output ports responsive to signals on said N interconnection network vector output leads. 
     
     
       25. The network of claim 12 further comprising a network output port and shift register means connected to said network output port and responsive to said interconnection network vector output leads. 
     
     
       26. The network of claim 1 further comprising network output leads connected to said interconnection network interface leads. 
     
     
       27. The network of claim 26 further comprising an auxiliary network, responsive to said K output ports of said decision network, for developing signals for additional output leads of said network. 
     
     
       28. A network for selecting a best match for an applied input signal having N components from among a stored set of M template signals having N components, where N, and M are integers, comprising: a first template network having N inputs and M outputs, with connection strength means for each input i for affecting the output of each output j, i and j being integers in the range 1 to N and 1 to M, respectively; and   threshold means responsive to said M outputs for applying a threshold to said M outputs,   wherein said connection strength means between an output j and the N inputs correspond to one of said stored templates and to no other of said stored templates.   
     
     
       29. The network of claim 28 wherein said connection strength means between input i and output j increases current in one direction along said output when said input is at a first logic level. 
     
     
       30. The network of claim 28 wherein said connection strength means between input i and output j increases current in one direction along said output when said input is at a first logic level and diminishes current in said direction along said output when said input is at a second logic level. 
     
     
       31. The network of claim 28 wherein said connection strength means between input i and output j is either E (excitatory) or I (inhibitory) connection, were an E connection increases current in one direction along said output when said input is at a first logic level, and an I connection diminishes current in said direction along said output wherein said input is at said first logic level. 
     
     
       32. The network of claim 28 wherein said connection strength means between input i and output j is either E (excitatory), I (inhibitory), or D (don't care) connection, were an E connection increases current in one direction along said output when said input is at a first logic level, an I connection diminishes current in said direction along said output wherein said input is at said first logic level, and a D connection does not affect said current. 
     
     
       33. The network of claim 33 wherein the effect of an E connection is different in magnitude from the effect of an I connection. 
     
     
       34. The network of claim 28 wherein said threshold means includes means for different threshold to different ones of said M outputs. 
     
     
       35. The network of claim 28 wherein said threshold means is an M input M-flop for developing a set of M output signals, only one of which is at one logic level while the remaining M-1 output signals are at another logic level. 
     
     
       36. The network of claim 28, further comprising: a second template network having M inputs and at least N1 outputs with connection strength means for each input i for affecting the output of each output i, i and j being integers in the range 1 to N and 1 to M, respectively; and   means for connecting outputs of said second template network to inputs of said first template network.