Digital FIFO memory

Abstract

A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respectively, which are controlled by a basic clock signal (g1) and further signals. Thus FIFO memory makes it possible to pass an input data stream arriving at an input data rate (g2) through the FIFO memory in such a way that the output data stream appears at the output (da) at an output data rate (g3) momentarily different from the input data rate (g2). On a time average, however, the two data rates are equal, so that data can be written into and read from the FIFO memory simultaneously at different rates.

I claim: 
     
       1. A digital FIFO memory comprising: insulated-gate field-effect transistors and a memory cell array (zf) of n parallel signal channels (b1 . . . bn) having their inputs connected to the data input (de) of the memory and having their outputs coupled to the data output (da) of the memory;   each signal channel containing m series-connected, identical memory cells (c . . . ) each having an enable input; and   clock signals being applied to the memory cells in so that memory cells which are adjacent in the direction of signal flow are rendered conductive one after the other;   wherein the input of the respective signal channel is connected directly to the data input (de), and the output to the data output (da);   wherein a first clock driver (tt1), a second clock driver (tt2), and an mth clock driver (ttm-1, ttm) are associated with the n first memory cells (c . . . 1), the n second memory cells (c . . . 2), and the n mth memory cells (c . . . m-1, c . . . m), respectively;   wherein the m clock drivers (tt . . . ), which are identical in construction, are fed a reset signal (rs) and a basic clock signal (g1) whose frequency is greater than twice the maximum input data rate (g2);   wherein each clock driver (tt . . . ) has a reset input (rs), and data availability input line (ve) and a data availability output line (va), with the data availability input line (ve) of a clock driver (tt2) connected to the data availability output line (va) of the directly preceding clock driver (tt1), as well as a data request input line (re) and a data request output line (ra), with the data request input line (re) of a clock driver (tt1) connected to the data request output line (ra) of the following clock driver (tt2);   wherein the data availability input line (ve) of the first clock driver (tt1) has a signal applied thereto which indicates the presence of valid input data; and   wherein the data request input line of the last clock driver (ttm) has a signal applied thereto which indicates that a next data word has to be transferred to the output.   
     
     
       2. The digital FIFO memory of claim 1 wherein each memory cell is comprised of transistors of a single conductivity type, namely a transfer transistor (t) in series with a level regenerator (p), particularly a static inverter, with the gate of the transfer transistor (t) being the enable input. 
     
     
       3. The digital FIFO memory of claim 1 wherein each memory cell is comprised of CMOS transistors, namely a first P-channel transistor (p1), a second P-channel transistor (p2), a second N-channel transistor (n2), and a first N-channel transistor (n1) having their controlled current paths connected in series in this order between a positive supply voltage (+u) and the associated negative reference point (-u), with the gates of the first P-channel transistor and the first N-channel transistor connected together to form the input of the memory cell, that a clock signal (G1) derived from the output signal (ta) of the clock driver (tt . . . ) is applied to the gate of the second N-channel transistor (n2), that the clock signal inverse thereto (G2) is applied to the gate of the second P-channel transistor (p2), and that the junction point of the two transistors (p2, n2) is the output of the memory cell. 
     
     
       4. The digital FIFO memory of claim 1 wherein each memory cell is comprised of transistors of a single conductivity type, namely a series combination formed by the controlled current paths of a first memory-cell transistor (ct1), a second memory-cell transistor (ct2), and a third memory-cell transistor (ct3) and beginning at the live terminal of a supply-voltage source (u), the gate of the third memory-cell transistor (ct3) being the input of the memory cell, the junction point of the first and second memory-cell transistors (ct1, ct2) forming the output of the memory cell, a first clock signal (F1) from the clock driver being applied to the gate of the first memory-cell transistor (ct1) and to the end of the series combination not connected to the supply-voltage source (u), and a second clock signal (F2) from the clock driver, which is delayed with respect to and overlaps the first clock signal (F1), being applied to the gate of the second memory-cell transistor (ct2). 
     
     
       5. The FIFO memory of claim 1 where in each signal channel (b1 . . . bn), the first memory cell (c . . . 1) is preceded by the demultiplex cell of a demultiplexer (dx), and the last memory cell (c . . . m) is followed by the multiplex cell of a multiplexer (mx). 
     
     
       6. The digital FIFO memory of claim 1: wherein each memory cell is comprised of transistors of a single conductivity type, namely a transfer transistor (t) in series with a level regenerator (p), particularly a static inverter, with the gate of the transfer transistor (t) being the enable input;   where in each signal channel (b1 . . . bn), the first memory cell (c . . . 1) is preceded by the demultiplex cell of a demultiplexer (dx), and the last memory cell (c . . . m) is followed by the multiplex cell of a multiplexer (mx); and   wherein each demultiplex cell is comprised of:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1), respectively, and the last input clock signal (en) being applied to all second additional memory cells (z . . . 2); and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1).   
     
     
       7. The digital FIFO memory of claim 1: wherein each memory cell is comprised of CMOS transistors, namely a first P-channel transistor (p1), a second P-channel transistor (p2), a second N-channel transistor (n2), and a first N-channel transistor (n1) having their controlled current paths connected in series in this order between a positive supply voltage (+u) and the associated negative reference point (-u), with the gates of the first P-channel transistor and the first N-channel transistor connected together to form the input of the memory cell, that a clock signal (G1) derived from the output signal (ta) of the clock driver (tt . . . ) is applied to the gate of the second N-channel transistor (n2), that the clock signal inverse thereto (G2) is applied to the gate of the second P-channel transistor (p2), and that the junction point of the two transistors (p2, n2) is the output of the memory cell;   where in each signal channel (b1 . . . bn), the first memory cell (c . . . 1) is preceded by the demultiplex cell of a demultiplexer (dx), and the last memory cell (c . . . m) is followed by the multiplex cell of a multiplexer (mx); and   wherein each demultiplex cell comprises:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1) respectively, and the last input clock signal (en) being applied to all second additional memory cells (z . . . 2), and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1).   
     
     
       8. The digital FIFO memory of claim 1: wherein each memory cell is comprised of transistors of a single conductivity type, namely a transfer transistor (t) in series with a level regenerator (p), particularly a static inverter, with the gate of the transfer transistor (t) being the enable input;   wherein each demultiplex cell comprises:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1), respectively, and the last input clock signal (en) being applied to all second additional memory cells (z . . . 2); and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1), and   wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and an additional transfer transistor (zt . . . ), with the third additional memory cell (z . . . 3) being of the same design as the memory cells (c . . . ), and the transfer transistor in the third additional memory cell of the first signal channel (b1) omitted;   the gates of the transfer transistors of the multiplex cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3) of the second to the last signal channel (b2 . . . bn), and the first, second, next-to-last, and last output clock signals (s1, s2, sn-1), sn) being applied to the first, second, next-to-last, and last additional transfer transistors (zt . . . ), respectively; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1).   
     
     
       9. The digital FIFO memory of claim 1: wherein each memory cell is comprised of CMOS transistors, namely a first P-channel transistor (p1), a second P-channel transistor (p2), a second N-channel transistor (n2), and a first N-channel transistor (n1) having their controlled current paths connected in series in this order between a positive supply voltage (+u) and the associated negative reference point (-u), with the gates of the first P-channel transistor and the first N-channel transistor connected together to form the input of the memory cell, that a clock signal (G1) derived from the output signal (ta) of the clock driver (tt . . . ) is applied to the gate of the second N-channel transistor (n2), that the clock signal inverse thereto (G2) is applied to the gate of the second P-channel transistor (p2), and that the junction point of the two transistors (p2, n2) is the output of the memory cell;   wherein each demultiplex cell comprises:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1), respectively, and the last input clock signal (en) being applied to all second addtional memory cells (z . . . 2); and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1); and   wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and a fourth additional memory cell (Z . . . 4) of the same design as the memory cells (c . . . ), with the fourth additional memory cell of the first signal channel (b1) omitted;   the enable inputs of these two additional memory cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3), and the second, next-to-last, and last output clock signals (s2, sn-1, sn) being applied to the fourth additional memory cells (z . . . 4) of the second to the last signal channel (b2 . . . bn), respectively;   in the first signal channel (b1), the first additional memory cell (z11) is preceded by a static inverter (si) implemented in the same technology (e.g., N-channel, CMOS) as the memory cells; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1).   
     
     
       10. The digital FIFO memory of claim 1: wherein each memory cell is comprised of transistors of a single conductivity type, namely a series combination formed by the controlled current paths of a first memory-cell transistor (ct1), a second memory-cell transistor (ct2), and a third memory-cell transistor (ct3) and beginning at the live terminal of a supply-voltage source (u), the gate of the third memory-cell transistor (ct3) being the input of the memory cell, the junction point of the first and second memory-cell transistors (ct1, ct2) forming the output of the memory cell, a first clock signal (F1) from the clock driver being applied to the gate of the first memory-cell transistor (ct1) and to the end of the series combination not connected to the supply-voltage source (u), and a second clock signal (F2) from the clock driver, which is delayed with respect to and overlaps the first clock signal (F1), being applied to the gate of the second memory-cell transistor (ct2);   wherein each demultiplex cell comprises:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1), respectively, and the last input clock signal (en) being applied to all second additional memory cells (z . . . 2); and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1), and   wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and an additional transfer transistor (zt . . . ), with the third additional memory cell (z . . . 3) being of the same design as the memory cells (c . . . ), and the transfer transistor in the third additional memory cell of the first signal channel (b1) omitted;   the gates of the transfer transistors of the multiplex cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3) of the second to the last signal channel (b2 . . . bn), and the first, second, next-to-last, and last output clock signals (s1, s2, sn-1), sn) being applied to the first, second, next-to-last, and last additional transfer transistors (zt . . . ), respectively; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1).   
     
     
       11. The digital FIFO memory of claim 1: wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and an additional transfer transistor (zt . . . ), with the third additional memory cell (z . . . 3) being of the same design as the memory cells (c . . . ), and the transfer transistor in the third additional memory cell of the first signal channel (b1) omitted;   the gates of the transfer transistors of the multiplex cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3) of the second to the last signal channel (b2 . . . bn), and the first, second, next-to-last, and last output clock signals (s1, s2, sn-1), sn) being applied to the first, second, next-to-last, and last additional transfer transistors (zt . . . ), respectively; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1);   wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn).   
     
     
       12. The digital FIFO memory of claim 1: wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and a fourth additional memory cell (Z . . . 4) of the same design as the memory cells (c . . . ), with the fourth addtiional memory cell of the first signal channel (b1) omitted;   the enable inputs of these two additional memory cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3), and the second, next-to-last, and last output clock signals (s2, sn-1, sn) being applied to the fourth additional memory cells (z . . . 4) of the second to the last signal channel (b2 . . . bn), respectively;   in the first signal channel (b1), the first additional memory cell (z11) is preceded by a static inverter (si) implemented in the same technology (e.g., N-channel, CMOS) as the memory cells; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1);   wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn).   
     
     
       13. The digital FIFO memory of claim 1: wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and an additional transfer transistor (zt . . . ), with the third additional memory cell (z . . . 3) being of the same design as the memory cells (c . . . ), and the transfer transistor in the third additional memory cell of the first signal channel (b1) omitted;   the gates of the transfer transistors of the multiplex cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3) of the second to the last signal channel b2 . . . bn), and the first, second, next-to-last, and last output clock signals (s1, s2, sn-1), sn) being applied to the first, second, next-to-last, and last additional transfer transistors (zt . . . ), respectively; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1);   wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn);   wherein the basic clock signal (g1), the input data rate (g2), and the output data rate (g3) are non-overlapping two-phase signals (f1, f1q; f2, f2q; f3, f3q) of corresponding frequency, the first (f . . . ) of each each of which leads the second (f . . . q).   
     
     
       14. The digital FIFO memory of claim 1: wherein each memory cell is comprised of transistors of a single conductivity type, namely a transfer transistor (t) in series with a level regenerator (p), particularly a static inverter, with the gate of the transfer transistor (t) being the enable input; and   wherein each demultiplex cell is comprised of:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1), respectively, and the last input clock signal (en) being applied to all second additional memory cells (z . . . 2); and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1);   wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn);   wherein the basic clock signal (g1), the input data rate (g2), and the output data rate (g3) are non-overlapping two-phase signals (f1, f1q; f2, f2q; f3, f3q) of corresponding frequency, the first (f . . . ) of each each of which leads the second (f . . . q);   where in the N-channel clock driver (tt . . . ):   the data availability input line (ve) is connected to the input of a first inverter (i1) having its output coupled to the first input of a NAND gate (ng);   the data availability output line (va) is connected to the output of a first dynamic memory stage (sp1) comprising of three transistors (=differential transistors) (d11, d21, d31) connected in the manner of a differential amplifier between the positive terminal (+u) and the negative terminal (-u) of a DC supply voltage source, which output is the junction point of the control current paths of the differential transistors, and to the second input of the NAND gate (ng);   the gate of the first differential transistor (d11) is the reset input (rs), and the data request input line (re) is connected to the gate of the second differential transistor (d21);   the data request output line (ra) is connected to the output of a clock-switching stage (ss0), to the gate of the third differential transistor (d31), and to the clock output (ta); and   the output of the NAND gate (ng) is connected via the controlled current path of a series transistor (1t), to whose gate the second two-phase signal f1q) of the first basic clock signal (g1) is applied, to the input of the clock-switching stage (ss).   
     
     
       15. The digital FIFO memory of claim 1: wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn);   wherein a N-channel circuit for the second ring counter (rz2) is comprised of a plurality of stages and each stage comprises:   a master-slave D flip-flop (ff1 . . . ffn) and an additional clock-switching stage (ss1 . . . ssn), the slave portion of the flip-flop (ff1 . . . ffn) having an R input and an S input;   to Qq output of the flip-flop (ff . . . ) is connected to the input of the additional clock-switching stage (ss1 . . . ssn);   the first two-phase signal (fe) of the output data rate (g3) is applied to the additional clock-switching stage (ss1 . . . ssn);   the output of the additional clock-switching stage (ss1 . . . ssn) is the output for the respective output clock signal (s1 . . . sn);   the reset signal (rs) is applied to the S input of the first flip-flop (ff1) and to the R inputs of the second to the nth flip-flop (ff2 . . . ffn);   the flip-flops (ff . . . ) are connected in a ring circuit by coupling the respective Q output to the D input of the following flip-flop; and   the output of the first additional clock-switching stage (ss1) is connected to the data request output line (ra) of the nth clock driver (ttn).   
     
     
       16. The digital FIFO memory of claim 1: wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn),   wherein the N-channel circuit for the first ring counter (rz1) has a plurality of stages and each stage comprises:   a master-slave D flip-flop (ff . . . ) having an R input and an S input at the slave portion;   an additional clock-switching stage (ss . . . ) having its first input connected to the Qq output of the flip-flop (ff . . . ) and having the first two-phase signal (f2) of the input data rate (g2) applied to its second input; and   a second dynamic memory stage (sp2) comprising of three transistors (=differential transistors) (d12, d22, d32) connected in the manner of a differential amplifier between the positive and negative terminals of the DC supply voltage source;   the reset signal (rs) is applied to the S input of the first flip-flop (ff1), to the R input of the second to the nth flip-flop (ff2 . . . ffn), and to the gate of the first differential transistor (d12);   the second two-phase signal (f2q) of the input data rate (g2) is applied to the clock inputs of the flip-flops (ff . . . );   the flip-flops (ff . . . ) are connected in a ring circuit by coupling the respective Q output to the D input of the following flip-flop;   connected to the gate of the second differential transistor (d22) is the data request input line (re) of the first clock driver (tt1) and the junction point of the three differential transistors with the data availability output line (va) of the first clock driver (tt1), and   the gate of the third differential transistor (d32) is connected to the output of the last additional-clock switching stage (ssn).   
     
     
       17. The digital FIFO memory of claim 14: wherein the N-channel clock-switching stage (ss . . . ) comprises:   a first transistor (t1) and a second transistor (t2) having their controlled current paths connected in series between the respective first two-phase signal (f2, f3) and the negative terminal (-u);   a third transistor (t3) and a second inverter (i2) are connected between the input of the clock-switching stage (ss . . . ) and the gate of the first transistor (t1);   the input of the clock-switching stage is connected to the gate of the second transistor (t2);   the gate of the third transistor (t3) is connected to the positive terminal (+u) of the supply voltage source; and   the output of the clock-switching stage is the junction point of the two transistors (t1, t2).   
     
     
       18. The digital FIFO memory of claim 1: wherein each memory cell is comprised of transistors of a single conductivity type, namely a series combination formed by the controlled current paths of a first memory-cell transistor (ct1), a second memory-cell transistor (ct2), and a third memory-cell transistor (ct3) and beginning at the live terminal of a supply-voltage source (u), the gate of the third memory-cell transistor (ct3) being the input of the memory cell, the junction point of the first and second memory-cell transistors (ct1, ct2) forming the output of the memory cell, a first clock signal (F1) from the clock driver being applied to the gate of the first memory-cell transistor (ct1) and to the end of the series combination not connected to the supply-voltage source (u), and a second clock signal (F2) from the clock driver, which is delayed with respect to and overlaps the first clock signal (F1), being applied to the gate of the second memory-cell transistor (ct2); and   wherein each demultiplex cell is comprised of:   a series combination of a first additional memory cell (z . . . 1) and a second additional memory cell (z . . . 2) having the same internal circuit as the memory cells, with the enable input of the first additional memory cell (zn1) in the demultiplex cell of the last signal channel (bn) connected to a potential (vo) which keeps the input of the first additional memory cell (zn1) constantly open;   the enable inputs of the other first additional memory cells are controlled by n successively acting input clock signals (e . . . ) based on the input data rate (g2), with the first, second, and next-to-last input clock signals (e1, e2, en-1) being applied to the first additional memory cells (z . . . 1) in the first signal channel (b1), the second signal channel (b2), and the next-to-last signal channel (bn-1), respectively, and the last input clock signal (en) being applied to all second additional memory cells (z . . . 2); and   the input data rate (g2) is less than or equal to half the n-fold frequency of the basic clock signal (g1);   wherein each multiplex cell is formed by a series combination of a third additional memory cell (z . . . 3) and a fourth additional memory cell (Z . . . 4) of the same design as the memory cells (c . . . ), with the fourth additional memory cell of the first signal channel (b1) omitted;   the enable inputs of these two additional memory cells are controlled by output clock signals (s . . . ) based on the output data rate (g3), with the first output clock signal (s1) being applied to the third additional memory cells (z . . . 3), and the second, next-to-last, and last output clock signals (s2, sn-1, sn) being applied to the fourth additional memory cells (z . . . 4) of the second to the last signal channel (b2 . . . bn), respectively;   in the first signal channel (b1), the first additional memory cell (z11) is preceded by a static inverter (si) implemented in the same technology as the memory cells; and   the output data rate (g3) is less than or equal to half the n-fold frequency of the basic clock signal (g1);   wherein the basic clock signal (g1) is the shift signal for a first n-stage ring counter (rz1);   whose stage outputs provide the n input clock signals (e . . . );   to which the reset signal (rs) is applied;   which is connected to the data request output line (ra) of the first clock driver (tt1); and   in which the output of the last stage is coupled to the data availability input line (ve) of the first clock driver (tt1); and   that the output data rate (g3) is the shift signal for a second ring counter (rz2);   whose stage outputs provide the n output clock signals(s . . . );   to which the reset signal (rs) is applied; and   in which the output of the first stage is coupled to the data request input line (re) of the last clock driver (ttn);   where in the N-channel CMOS clock driver (tt . . . ):   the data availability input line (ve) is connected to one input of a NOR gate (nr) clocked by two clock signals;   connected between the supply voltage (+u) and its reference point (-u) is the series combination of a second P-channel transistor (pp2), a third P-channel transistor (pp3), and a third N-channel transistor (nn3), with the gate of the second P-channel transistor (pp2) connected to the output of the NOR gate (nr), and the junction point of the two third transistors connected through a second static inverter (ci2) to the output for the second clock signal (F2);   the output of the NOR gate (nr) is connected to the clock input of an inverter (ei) clocked by a single clock signal;   the output of this inverter (ei) is connected to the gate of the first P-channel transistor (pp1) and, through a third static inverter (ci3), to the gate of the third N-channel transistor (nn3) and to the output for the first clock signal (F1); and   from the basic clock signal (g1), a first pair (m1, m1q) and a second pair (m2, m2q) of nonoverlapping CMOS clock signals are derived, the first signal (m1) of the first pair being applied to the gate of the inverter (ei) clocked by a single clock signal, the first signal (m2) of the second pair being applied to the gate of the third P-channel transistor (pp3), and the second pair (m2, m2q) being applied to the NOR gate (nr).