Circuit arrangement for designational reading of information of a bit group oriented, continuous information stream at an ISDN-oriented interface

Abstract

The reading times for a designational reading of information communicated via an ISDN-oriented interface are formed for a recording device and transmitted thereto with the assistance of a circuit arrangement, being formed from bit clock signals and bit group clock signals, which define the boundaries of the bit groups comprising 32 bits, that are present in an ISDN-oriented interface. The reading times present in the form of bit clock pulses inform the recording device of the times at which the information are to be read and subsequently stored. The circuit arrangement contains a shift register that is formed by a plurality of registers corresponding in number to the plurality of bits of a bit group, a reset device that is realized, for example, by an inverter and a switch, and also contains an AND gate and a plurality of switch devices whose setting determines which information are, respectively, bits of a bit group are to be read and stored.

We claim: 
     
       1. A circuit arrangement for generating signals corresponding to the read points in time necessary to allow a recording unit to designationally read information contained in two serial, bit-oriented ISDN information signal streams respectively transmitted via communication lines of first and second ISDN-oriented interfaces respectively disposed in first and second ISDN equipment stations, said first and second ISDN-oriented interfaces facilitating communication between said first and second ISDN equipment stations, each of said two serial, bit-oriented ISDN information signal streams formed as a continuous sequence of bit groups, each bit group having a prescribed plurality of bits arranged in sub-groups or channels having a defined plurality of bits with a defined information content, said first ISDN-oriented interface providing a bit clock signal and a bit group clock signal to said second ISDN-oriented interface, said arrangement comprising: a shift register having a clock input and a plurality of storage locations respectively dedicated to said prescribed plurality of bits of a bit group, said shift register further having a shift-set input connected to receive said bit group clock signal;   reset means connecting said shift-set input to said bit group clock signal and operable to generate a shift register reset signal from said bit group clock signal;   said shift register further having a plurality of parallel inputs corresponding to said plurality of storage locations, each of said parallel inputs being connectible to a voltage potential representing two binary conditions;   switch means connecting said inputs to said voltage potential;   an AND logic gate connected to receive said shift register output and said bit clock signal, said AND logic gate having an output; and   a recording unit connected to said output of said AND gate for recording the informational contents of those bits of the bit determined by said switch means.   
     
     
       2. The arrangement of claim 1, wherein said storage locations of said shift register correspond in number to half the number of bits of a bit group, and wherein said reset means comprises an inverter and a switch, whereby said inverter is insertable into or removable from said connection from said shift-set input to said clock line dependent on the bit group for which the read points in time are to be determined. 
     
     
       3. The arrangement of claim 2, wherein two ISDN information channels are provided, one ISDN signaling channel and a monitoring telemetry channel are assigned to the bit groups. 
     
     
       4. The arrangement of claim 3, wherein said shift register comprises serially-connected, edge-triggered J/K flip-flops. 
     
     
       5. The arrangement of claim 4, wherein said switch means are toggle switches. 
     
     
       6. The arrangement of claim 5, wherein said shift register, said reset means, said switch means and said AND logic gate are arranged in an equipment housing as a single unit, all connections to or from the ISDN-oriented interface and said equipment housing connected thereto via releasable connections. 
     
     
       7. An apparatus for generating control signals coincident with designated data bits in a serial ISDN information stream transmitted between two ISDN-oriented interfaces respectively disposed in two communicating ISDN equipment stations, said serial ISDN information stream formed as a continuous sequence of bit groups, each bit group having a prescribed plurality of bit sub-groups each having a defined plurality of bits, one of said two ISDN-oriented interfaces providing a bit clock signal at a first clock rate and a bit group clock signal at a second clock rate, said signals coincident with said designated data bits being used by a recording unit, said apparatus comprising: a shift register having a clock input, a shift-set input, and a plurality of storage locations equal in number to said defined plurality of bits in a single bit sub-group of said prescribed plurality of bit sub-groups, said storage locations each having a respective input;   shift control means responsive to said bit group clock signal and said bit clock signal for generating a first signal from said bit clock signal coincident with all data bits in said serial ISDN information stream, said first signal supplied to said clock input of said shift register, and for generating a second signal from said bit group clock signal coincident with an occurrence of a bit-subgroup having said designated data bits, said second signal supplied to said shift-set input of said shift register;   switch means for selectively supplying logic level signals to each of said respective inputs of said storage locations, said logic level signals having a first and second state, said first logic state selectively supplied to said respective inputs corresponding to bit positions of said designated data signals in said bit-subgroup having said data bits, said shift register means shifting said logic level signals to an output of said shift register means in response to said first and second signals supplied from said shift control means; and   coincidence detection means for generating said control signals to said recording unit in response to coincidence between said first signal and an occurrence of said first logic level at said output of said shift register.   
     
     
       8. An apparatus as recited in claim 7, wherein said shift control means comprises dividing means for generating said first signal by dividing said first clock rate of said bit clock signal. 
     
     
       9. An apparatus as recited in claim 7, wherein said shift control means comprises: an inverter having an input receiving said bit group clock signal and an output;   a toggle switch having a first terminal connected to said output of said inverter, a second terminal connected to said bit group clock, and a pole connected to said shift-set input of said shift register.   
     
     
       10. An apparatus as recited in claim 9, wherein said shift control means further comprises dividing means for generating said first signal by dividing said first clock rate of said bit clock signal. 
     
     
       11. An apparatus as recited in claim 7, wherein said switch means comprises a plurality of toggle switches each having a first terminal connected to a first voltage source corresponding to said first logic level, a second terminal connected to a second voltage corresponding to said second logic level, and a pole terminal connected to a respective input of one of said storage locations. 
     
     
       12. An apparatus as recited in claim 7, wherein said shift register comprises serially-connected, edge-triggered J/K flip-flops. 
     
     
       13. An apparatus as recited in claim 7, wherein said coincidence detection means comprises an AND gate having a first input connected to said output of said shift register, a second input connected to said first control signal of said shift control means, and an output supplied to said recording unit. 
     
     
       14. An apparatus for generating control signals coincident with designated data bits in a serial ISDN information stream transmitted between two ISDN-oriented interfaces respectively disposed in two communicating ISDN equipment stations, said serial ISDN information stream formed as a continuous sequence of bit groups, each bit group having a prescribed plurality of bits arranged in sub-groups, one of said two ISDN-oriented interfaces providing a bit clock signal at a first clock rate and a bit group clock signal at a second clock rate, said signals coincident with said designated data bits being used by a recording unit, said apparatus comprising: a shift register having a clock input, a shift-set input, and a plurality of storage locations equal in number to said prescribed plurality of bits in a single bit group, said storage locations each having a respective input;   shift control means responsive to said bit group clock signal and said bit clock signal for generating a first signal from said bit clock signal coincident with all data bits in said serial ISDN information stream, said first signal supplied to said clock input of said shift register, and for generating a second signal from said bit group clock signal coincident with an occurrence of a bit group having said designated data bits, said second signal supplied to said shift-set input of said shift register;   switch means for selectively supplying logic level signals to each of said respective inputs of said storage locations, said logic level signals having a first and second state, said first logic state selectively supplied to said respective inputs of said storage locations corresponding to bit positions of said designated data signals in said bit group, said shift register means shifting said logic level signals to an output thereof in response to said first and second signals supplied from said shift control means; and   coincidence detection means for generating said control signals to said recording unit in response to coincidence between said first signal and an occurrence of said first logic level at said output of said shift register.   
     
     
       15. An apparatus as recited in claim 14, wherein said shift control means comprises dividing means for generating said first signal by dividing said first clock rate of said bit clock signal. 
     
     
       16. An apparatus as recited in claim 14, wherein said switch means comprises a plurality of toggle switches each having a first terminal connected to a first voltage source corresponding to said first logic level, a second terminal connected to a second voltage corresponding to said second logic level, and a pole terminal connected to a respective input of one of said storage locations. 
     
     
       17. An apparatus as recited in claim 14, wherein said shift register comprises serially-connected, edge-triggered J/K flip-flops. 
     
     
       18. An apparatus as recited in claim 14, wherein said coincidence detection means comprises an AND gate having a first input connected to said output of said shift register, a second input connected to said first control signal of said shift control means, and an output supplied to said recording unit.