Rectifier circuit provoding compression of the dynamic range of the output voltage

Abstract

The output terminals of a three-phase, wye-connected AC source, whose voltage varies over a wide dynamic range, are connected to a pair of DC voltage buses through a pair of oppositely poled, half-wave rectifier networks and a pair of switches. Taps uniformly positioned on the phase windings are brought out through another half-wave rectifier network directly to one bus, and the source neutral is connected directly to the other bus through a diode. A control circuit, operating in response to the DC voltage appearing across the buses, opens and closes the switches to selectively switch the rectifier networks and diode in and out so as to limit the DC voltage to a predetermined, compressed dynamic range.

Having described the invention, what is claimed as new and desired to be secured by Letter Patent is: 
     
       1. A rectifier circuit comprising, in combination: A. an AC source subject to variation in voltage over a large dynamic range, said source including (1) a winding in which a voltage is induced having at least first and second winding sections with corresponding one ends thereof commonly connected to a neutral point and corresponding other ends thereof respectively connected to separate AC output terminals; and   (2) each said first and second winding sections having a tap at a location uniformly spaced from said neutral point;     B. first and second DC voltage buses;   C. first rectifier means poled in a first direction and having input terminals respectively connected between said AC output terminals and a first DC terminal;   D. second rectifier means poled in a second direction opposite said first direction and having input terminals respectively connected between said AC output terminals and a second DC terminal;   E. a first switch connecting said first DC terminal to said first DC bus;   F. a second switch connecting said second DC terminal to said second DC bus;   G. third rectifier means poled in said first direction and having input terminals respectively connected between said taps and said first DC bus;   H. fourth rectifier means poled in said second direction and connecting said neutral point to said second DC bus; and   I. a control circuit operating in response to the DC output voltage across said first and second DC buses for selectively opening and closing said first and second switches such as to limit the DC output voltage to a dynamic range smaller than the dynamic voltage range of said AC source.   
     
     
       2. The rectifier circuit defined in claim 1, wherein said control circuit is structured for effecting (1) a first switch mode wherein both said first and second switches are closed to provide said DC output voltage as a full-wave rectification of the AC voltages appearing on said first and second winding sections at said AC output terminals thereof,   (2) a second switch mode wherein said first switch is closed and said second switch is open to provide said DC output voltage as a half-wave rectification of the AC voltages appearing on said first and second winding sections between said neutral point and said AC output terminals thereof,   (3) a third switch mode wherein said first switch is open and said second switch is closed to provide said DC output voltage as a half-wave rectification of the AC voltages appearing on said first and second winding sections between said taps and said AC output terminals thereof, and   (4) a fourth switch mode wherein both said first and second switches are open to provide said DC output voltage as a half-wave rectification of the AC voltages appearing on said first and second winding sections between said taps and said neutral point.   
     
     
       3. The rectifier circuit defined in claim 2, wherein said control circuit further is structured to step between successive switch modes from said first to said second to said third to said fourth switch modes in ascending order in response to a rising DC output voltage and to step between said successive switch modes in descending order in response to a falling DC output voltage. 
     
     
       4. The rectifier circuit define in claim 3, wherein said control circuit includes first means for establishing an upper DC voltage threshold and second means for establishing a lower DC voltage threshold, said first means initiating a step from one of said switch modes to the next said switch mode in ascending order each time a rising DC output voltage reaches said upper voltage threshold, and said second means initiates a step from one of said switch modes to the next said switch mode in descending order each time a falling DC output voltage reaches said lower voltage threshold. 
     
     
       5. The rectifier circuit defined in claim 4, wherein the difference between said upper and lower voltage thresholds of the control circuit limits the maximum change in said DC output voltage before stepping to another switch mode. 
     
     
       6. The rectifier circuit defined in claim 5, wherein said control circuit further includes a counter responsive to said first means for changing its content one count in one direction each time said DC output voltage reaches said upper DC voltage threshold and responsive to said second means for changing its said content one count in a direction opposite said one direction each time said DC output voltage reaches said lower DC voltage threshold, and gating means responsive to said counter content for selectively effecting said first, second, third and fourth switch modes. 
     
     
       7. The rectifier circuit defined in claim 6, wherein said control circuit further includes third means for establishing a maximum DC voltage threshold above said upper DC voltage threshold and fourth means for establishing a minimum DC voltage threshold below said lower DC voltage threshold, said third means effecting said fourth switch mode in the event said DC output voltage rises to said maximum DC threshold voltage, and said fourth means effecting said first switch mode in the event said DC output voltage falls to said minimum DC voltage threshold. 
     
     
       8. The rectifier circuit defined in claim 7, wherein said third means conditions said gating means to effect said fourth switch mode regardless of said counter content in the event said DC output voltage rises to said maximum DC voltage threshold, and said fourth means zeros said counter content to effect said first switch mode in the event said DC output voltage falls to said minimum DC voltage threshold. 
     
     
       9. The rectifier circuit define in claim 8, wherein said AC source is a three-phase source having first, second and third winding sections connected to wye configuration to said neutral point and each having a separate said tap at a uniformly spaced location from said neutral point. 
     
     
       10. The rectifier circuit defined in claim 9, wherein each said tap is located in each said winding section relative to said neutral point at a point approximately one-third of the length of said winding section extending from said neutral point to said AC output terminal thereof. 
     
     
       11. A polyphase rectifier circuit comprising, in combination: A. a polyphase AC source subject to variation in voltage over a large dynamic range, said source including (1) three phase windings in which a voltage is induced having corresponding one ends thereof commonly connected to a neutral point and corresponding other ends thereof respectively connected to separate AC output terminals; and   (2) each said phase winding having a tap at location uniformly spaced from said neutral point;     B. first and second DC voltage buses;   C. a first set of three half-wave rectifiers poled in a first direction and having separate input terminals respectively connected between said AC output terminals and a first common DC terminal;   D. a second set of three half-wave rectifiers poled in a second direction opposite said first direction and having separate input terminals respectively connected between said AC output terminals and a second common DC terminal;   E. a first switch connecting said first DC terminal to said first DC bus;   F. a second switch connecting said second DC terminal to said second DC bus;   G. a third set of three half-wave rectifiers poled in said first direction and having separate input terminals respectively connected between said taps and said first DC bus;   H. a fourth half-wave rectifier poled in said second direction and connecting said neutral point to said second DC bus; and   I. a control circuit operating in response to the DC voltage across said first and second DC buses for selectively opening and closing said first and second switches such as to limit the DC output voltage to a dynamic range smaller than the dynamic voltage range of said AC source.   
     
     
       12. The polyphase rectifier circuit defined in claim 11, wherein said control circuit is structured for effecting (1) a first switch mode wherein both said first and second switches are closed to provide said DC output voltage as a full-wave rectification of the AC voltages appearing on said windings at said AC output terminals thereof,   (2) a second switch mode wherein said first switch is closed and said second switch is open to provide said DC output voltage as a half-wave rectification of the AC voltage appearing on said windings between said neutral point and said AC output terminals thereof,   (3) a third switch mode wherein said first switch is open and said second switch is closed to provide said DC output voltage as a half-wave rectification of the AC voltages appearing on said windings between said taps and said AC output terminals thereof, and   (4) a fourth switch mode wherein both said first and second switches are open to provide said DC output voltage as a half-wave rectification of the AC voltages appearing on said windings between said taps and said neutral point.   
     
     
       13. The polyphase rectifier circuit defined in claim 12, wherein said control further is structured to step between successive switch modes in an ascending order in response to a rising DC output voltage and to step between said successive switch modes in a descending order in response to a falling DC output voltage. 
     
     
       14. The polyphase rectifier circuit defined in claim 13, wherein said control circuit includes first means for establishing an upper DC voltage threshold and second means for establishing a lower DC voltage threshold, said first means initiating a step from one of said switch modes to the next said switch mode in ascending order each time a rising DC output voltage reaches said upper voltage threshold, and said second means initiates a step from one of said switch modes to the next said switch mode in descending order each time a falling DC output voltage reaches said lower voltage threshold. 
     
     
       15. The polyphase rectifier circuit defined in claim 14, wherein the difference between said upper and lower voltage thresholds of the control circuit limits the maximum change in said DC output voltage before stepping to another switch mode. 
     
     
       16. The polyphase rectifier circuit defined in claim 15, wherein said control circuit further includes a counter responsive to said first means for changing its content one count in one direction each time said DC output voltage reaches said upper DC voltage threshold and responsive to said second means for changing its said content one count in a direction opposite said one direction each time said DC output voltage reaches said lower DC voltage threshold, and gating means responsive to said counter content for selectively effecting said first, second, third and fourth switch modes. 
     
     
       17. The polyphase rectifier circuit defined in claim 16, wherein said control circuit further includes third means for establishing a maximum DC voltage threshold above said upper DC voltage threshold and fourth means for establishing a minimum DC voltage threshold below said lower DC voltage threshold, said third means effecting said fourth switch mode in the event said DC output voltage rises to said maximum DC threshold voltage, and said fourth means effecting said first switch mode in the event said DC output voltage falls to said minimum DC voltage threshold. 
     
     
       18. The polyphase rectifier circuit defined in claim 17, wherein said third means conditions said gating means to effect said fourth switch mode regardless of said counter content in the event said DC output voltage rises to said maximum DC voltage threshold, and said fourth means zeros said counter content to effect said first switch mode in the event said DC output voltage falls to said minimum DC voltage threshold. 
     
     
       19. The polyphase rectifier circuit defined in claim 15, wherein each said tap is located in each said winding relative to said neutral point at a point approximately one-third of the length of said winding section extending from said neutral point to said AC output terminal thereof.