Referenceless ECL logic circuit

Abstract

An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

We claim: 
     
       1. A logic circuit comprising: a first NPN transistor and a second NPN transistor connected as a differential amplifier;   a third NPN transistor connected in parallel with said second transistor;   first driving means for driving said first and second NPN transistors with complementary signals having high and low levels; and   second driving means for driving said third NPN transistor with an output signal having a high level that is higher than the high levels of said complementary signals, and having a low level that is lower than the high levels of said complementary signals.   
     
     
       2. A logic circuit according to claim 1, wherein said second driving means includes: means for generating the low level of the output signal such that the low level is substantially equal to the low levels of said complementary signals.   
     
     
       3. A logic circuit according to claim 1, wherein said second driving means includes: means for generating the low level of the output signal such that the low level is lower than the low levels of the said complementary signals.   
     
     
       4. A logic circuit according to claim 1, wherein said second driving means includes: means for generating the low level of the output signal such that the low level is higher than the low levels of the said complementary signals.   
     
     
       5. A logic circuit according to claim 1, further comprising: a constant current source, and wherein   each of said first, second and third NPN transistors have emitters that are operatively connected to each other, and connected to said constant-current source.   
     
     
       6. A logic circuit according to claim 5, wherein said constant-current source comprises: a fourth transistor;   a resistor serially connected to an emitter electrode of said fourth transistor; and   means for providing a constant voltage to a base electrode of said fourth transistor.   
     
     
       7. A logic circuit according to claim 5, wherein said constant-current source comprises a resistor. 
     
     
       8. A logic circuit according to claim further comprising: a resistor operatively connected to receive a collector power source voltage and operatively connected to one of a collector of said first transistor and of said second transistor,   whereby a logic signal is output from said collector connected to said resistor.   
     
     
       9. A logic circuit according to claim 1, wherein said complementary signals have rise and fall times, and wherein said second driving means includes: means for generating the output signal so as to have a rise time and a fall time that are longer than those of said complementary signals.   
     
     
       10. A logic circuit according to claim 1, wherein said complementary signals have a frequency and wherein said second driving means includes: means for generating the output signal so as to have a frequency that is lower than that of said complementary signals.   
     
     
       11. A logic circuit comprising: a first PNP transistor and a second PNP transistor connected as a differential amplifier;   a third PNP transistor connected in parallel with said second transistor;   first driving means for driving said first and second PNP transistors with complementary signals having high and low levels; and   second driving means for driving said third PNP transistor with an output signal having a low level that is lower than the low levels of said complementary signals, and having a high level that is higher than the low levels of said complementary signals.   
     
     
       12. A logic circuit according to claim 11, wherein said second driving means includes: means for generating the high level of the output signal such that the high level is substantially equal to the high levels of said complementary signals.   
     
     
       13. A logic circuit according to claim 11, wherein said second driving means includes: means for generating the high level of the output signal such that the high level is higher than the high levels of said complementary signals.   
     
     
       14. A logic circuit according to claim 11, wherein said second driving means includes: means for generating said high level of the output signal such that the high level is lower than the high levels of said complementary signals.   
     
     
       15. A logic circuit according to claim 11, further comprising: a constant current source, and wherein   each of said first, second and third PNP transistors have emitters that are operatively connected to each other, and connected to said constant-current source.   
     
     
       16. A logic circuit according to claim 15, wherein said constant-current source comprises: a fourth transistor;   a resistor serially connected to an emitter electrode of said fourth transistor; and   means for providing a constant voltage to a base electrode of said fourth transistor.   
     
     
       17. A logic circuit according to claim 15, wherein said constant-current source comprises a resistor. 
     
     
       18. A logic circuit according to claim 11, further comprising: a resistor operatively connected to receive a collector power source voltage and operatively connected to one of a collector of said first transistor and of said second transistor,   whereby a logic signal is output from said collector connected to said resistor.   
     
     
       19. A logic circuit according to claim 11, wherein said complementary signals have rise and fall times, and wherein said second driving means includes: means for generating the output signal so as to have a rise time and a fall time that are longer than those of said complementary signals.   
     
     
       20. A logic circuit according to claim 11, wherein said complementary signals have a frequency and wherein said second driving means includes: means for generating the output signal so as to have a frequency that is lower than that of said complementary signals.   
     
     
       21. A logic circuit comprising: a first transistor and a second transistor connected as a differential amplifier;   a third transistor connected in parallel with said second transistor;   first driving means for driving said first and second transistors with complementary signals having high and low levels; and   second driving means for driving said third transistor with an output signal having a high level that is higher than the high levels of said complementary signals, and having a low level that is lower than the low levels of said complementary signals.   
     
     
       22. A logic circuit according to claim 21, further comprising: a constant current source, and wherein   each of said first, second and third transistors have emitters that are operatively connected to each other, and connected to said constant-current source.   
     
     
       23. A logic circuit according to claim 21, wherein said constant-current source comprises: a fourth transistor;   a resistor serially connected to an emitter electrode of said fourth transistor; and   means for providing a constant voltage to a base electrode of said fourth transistor.   
     
     
       24. A logic circuit according to claim 21, wherein said constant-current source comprises a resistor. 
     
     
       25. A logic circuit according to claim 21, further comprising: a resistor operatively connected to receive a collector power source voltage and operatively connected to one of a collector of said first transistor and of said second transistor,   whereby a logic signal is output from said collector connected to said resistor.   
     
     
       26. A logic circuit according to claim 21, wherein said complementary signals have a frequency and wherein said second driving means includes: means for generating the output signal so as to have a frequency that is lower than that of said complementary signals.   
     
     
       27. A logic circuit according to claim 21, wherein said complementary signals have rise and fall times, and wherein said second driving means includes: means for generating the output signal so as to have a rise time and a fall time that are longer than those of said complementary signals.   
     
     
       28. A logic circuit according to claim 20, wherein said complementary signals have a frequency and wherein said second driving means includes: means for generating the output signal so as to have a frequency that is lower than that of said complementary signals.