Data processor system and method

Abstract

A system and method for processing an extraordinarily large amount of data is configured using ordinary versatile computers of relatively slow data processing speed. Tasking is shared to plural computers or processors connected to a system bus; a shared storage device provided in common for these processors is made up of plural memory banks connected to the system bus; data transferred between the processors and the memory banks are divided into predetermined amounts of divisional data; the divisional data are processed simultaneously in parallel fashion; and each memory bank is occupied simultaneously in parallel fashion in response to each memory request from each processor. An arbitrator is provided for acting on a single memory request in accordance with a predetermined priority order in the case where plural memory requests are outputted simultaneously to the same memory bank.

What is claimed is: 
     
       1. A data processing system of the type having a system bus, including a bus clock, one or more data input means for inputting data, display means for displaying inputted data and processed data, storage means for storing the input data and the processed data, and shared storage means connected to each of the above means through the system bus, the system processing data as designated by the data input means, wherein the system comprises (a) a plurailty of memory bank means, each of which is connected to the system bus and which together constitute the shared storage means;   (b) a plurality of separate processor means provided for each of the data input means, the display means and the data storage means, respectively, for separately processing data for each of them, each of the separate processor means being connected to the system bus and being capable of generating a memory request command signal on the system bus for the purpose of transferring data between itself and any one of the memory bank means;   (c) arbitration means within the shared storage means which is responsive to a memory request command signal generated by one of the processor means for generating separate enable signals to acknowledge occupation of one of the memory bank means by the one processor means which generated the memory request; and   (d) data dividing means for dividing data transferred between the one processor means and the one memory bank means into predetermined groupings of divisional data and for processing each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion when a plurality of memory requests are out-putted simultaneously from a plurality of the processor means.   
     
     
       2. A data processing system of the type having a system bus, including a bus clock, one or more data input means for inputting data, display means for displaying inputted data and processed data, storage means for storing the input data and the processed data, and shared storage means connected to each of the above means through the system bus, the system processing data as designated by the data input means, wherein the system comprises (a) a plurality of memory bank means, each of which is connected to the system bus and which together constitute the shared storage means;   (b) a plurality of separate processor means provided for each of the data input means, the display means and the data storage means, respectively, for separately processing data for each of them, each of the separate processor means being connected to the system bus and being capable of generating a memory request command signal on the system bus for the purpose of transferring data between itself and any one of the memory bank means;   (c) arbitration means within the shared storage means which is responsive to a memory request command signal generated by one of the processor means for generating separate enable signals to acknowledge occupation of one of the memory bank means by the one processor means which generated the memory request, the arbitration means including means for generating a sequence of separate timing signals whose periods define "time slots" and allocating the time slots to the plurality of memory bank means in sequence and synchronously with the bus clock of the system bus so that for each memory bank means there is a corresponding time slot, and wherein the enable signals are generated during the corresponding time slots; and   (d) data dividing means for dividing data transferred between the one processor means and the one memory bank means into predetermined groupings of divisional data and for processing each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion when a plurality of memory requests are out-putted simultaneously from a plurality of the processor means and wherein the data dividing means transfers divisional data between the one processor means and the one memory bank means through the system bus during a predetermined number of time slots after the time slot allocated to the one memory bank means.   
     
     
       3. The data processing system as set forth in claim 2, wherein the data dividing means transfers divisional data to another one of the memory bank means through the system bus a predetermined number of time slots after a time slot corresponding to any of the memory bank means for which there is no outstanding memory request. 
     
     
       4. The data processing system as set forth in claim 3, wherein the arbitration means additionally generates at least one time slot ("non-allocated time slot") which is not allocated to any of the memory bank means and wherein the data dividing means transfers divisional data to the one memory bank means through the system bus a predetermined number of time slots after the non-allocated time slot. 
     
     
       5. The data processing system as set forth in claim 2, wherein the time slots are selected to have a time duration which is shorter than the time required by any one of the memory bank means to write or read data. 
     
     
       6. The data processing system as set forth in claim 2, wherein the time slots are selected to have a time duration which is shorter than the data processing time required by any one of the processor means to process the data read by it through the system bus. 
     
     
       7. The data processing system as set forth in claim 1, wherein the system bus comprises: (a) an address bus for transferring address data to designate an address of a memory location in the one memory bank means;   (b) a write data bus for transferring write data to be written in the memory location designated by the address data; and   (c) a read data bus for transferring data read from the memory location designated by the address data, and wherein the data corresponding to the one memory bank means are outputted to the address data bus, the write data bus and the read data bus at different times for the one memory bank means according the sequence of the allocated time slots.   
     
     
       8. The data processing system as set forth in claim 1, wherein the plurality of processor means is comprised of one or more microprocessors. 
     
     
       9. The data processing system as set forth in claim 1, wherein one or more of the memory bank means comprises a dynamic RAM. 
     
     
       10. The data processing system as set forth in claims 1, 2, 3, or 4, wherein the arbitrating means further comprises means for selecting, in accordance with a predetermined priority order with respect to each processor means, one of a plurality of memory requests which are outputted simultaneously from two or more processor means to the same memory bank means and for processing data corresponding to the memory request selected on the basis of the predetermined priority. 
     
     
       11. The data processing system as set forth in claim 10, wherein the arbitrating means comprises a lock function such that a selection of other memory requests is refused until divisional data corresponding to one of the priority-selected memory requests have been processed. 
     
     
       12. A method of processing data using a data processing system of the type having a bus clock, a system bus and an address bus, the method being of the type having the steps of inputting data, storing data, processing data, and displaying data wherein the improvement comprises the steps of: (a) storing data in a plurality of memory banks which are connected to each other by the system bus;   (b) separately processing data for each of the steps of inputting, storing, and displaying data, in separate data processors, each of the separate processing steps being carried out over the system bus, and outputting a memory request command signal on the system bus from one of the data processors for the purpose of transferring data between one of the memory banks and the one data processor;   (c) occupying the one memory bank while transferring data between the one processor and the one memory bank and generating an enable signal to acknowledge the occupation; and   (d) simultaneously outputting a plurality of memory requests from a plurality of processors, dividing data to be transferred between the processors and the memory banks into predetermined groupings of divisional data, and processing each divisional data in synchronization with the bus clock of the system bus and in simultaneous parallel fashion.   
     
     
       13. The data processing method as set forth in claim 12, wherein (a) the memory bank occupying step comprises the steps of generating a sequence of separate timing signals whose periods define "time slots" and allocating the time slots to the plurality of memory banks in sequence and synchronously with the bus clock of the system bus so that for each memory bank there is a corresponding time slot and generating the enable signals during the corresponding time slots, and wherein   (b) the data dividing step comprises transferring divisional data between the one processor and the one memory bank through the system bus during a predetermined number of time slots after the time slot allocated to the one memory bank.   
     
     
       14. The data processing method as set forth in claim 13, wherein the data dividing step comprises transferring divisional data to another one of the memory banks through the system bus a predetermined number of time slots after a time slot corresponding to any of the memory banks for which there is no outstanding memory request. 
     
     
       15. The data processing method as set forth in claim 14, wherein the arbitration additionally generates at least one time slot ("non-allocated time slot") which is not allocated to any of the memory banks and wherein the data dividing transfers divisional data to the one memory bank through the system bus a predetermined number of time slots after the non-allocated time slot. 
     
     
       16. The data processing method as set forth in claim 15, wherein the time slots are selected to have a time duration which is shorter than the time required by any one of the memory banks to write or read data. 
     
     
       17. The data processing method as set forth in claim 16, wherein the time slots are selected to have a time duration which is shorter than the data processing time required by any one of the processors to process the data read by it through the system bus. 
     
     
       18. The data processing method as set forth in claims 12, 13, 14, or 15, wherein the arbitrating step further comprises the steps of selecting, in accordance with a predetermined priority order with respect to each processor, one of a plurality of memory requests which are outputted simultaneously from two or more processor to the same memory bank and for processing data corresponding to the memory request selected on the basis of the predetermined priority. 
     
     
       19. The data processing method as set forth in claim 10, wherein the arbitrating step further comprises a lock step wherein the selection of other memory requests is refused until divisional data corresponding to one of the priority-selected memory requests have been processed.